PSD834F2-15M STMicroelectronics, PSD834F2-15M Datasheet - Page 72
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PSD834F2-15M
Manufacturer Part Number
PSD834F2-15M
Description
Manufacturer
STMicroelectronics
Datasheet
1.PSD834F2-15M.pdf
(95 pages)
Specifications of PSD834F2-15M
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Package Type
PQFP
Mounting
Surface Mount
Pin Count
52
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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PSD834F2V
Figure 35. Input to Output Disable / Enable
Table 43. CPLD Combinatorial Timing
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
72/95
t
t
t
t
t
t
Symbol
PD
EA
ER
ARP
ARPW
ARD
CPLD Input Pin/
Feedback to CPLD
Combinatorial Output
CPLD Input to CPLD
Output Enable
CPLD Input to CPLD
Output Disable
CPLD Register Clear
or
Preset Delay
CPLD Register Clear
or
Preset Pulse Width
CPLD Array Delay
Parameter
ENABLE/DISABLE
INPUT TO
OUTPUT
INPUT
Conditions
macrocell
Any
Min Max Min Max Min Max
25
tER
-10
40
43
43
40
25
30
-15
45
45
45
43
29
35
tEA
-20
50
50
50
48
33
Aloc
+ 4
+ 4
PT
AI02863
Turbo
+ 20
+ 20
+ 20
+ 20
+ 20
Off
Slew
rate
– 6
– 6
– 6
– 6
1
Unit
ns
ns
ns
ns
ns
ns
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