LSI53CF92A LSI, LSI53CF92A Datasheet - Page 115

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

When these conditions are true, the chip halts with DREQ asserted. If
the chip is in Synchronous Transfer mode when halted, some ACK/
responses from the SCSI bus may not have been received and remain
outstanding. Upon receiving the Abort DMA command, the chip resets
the DMA interface, including the DREQ output pin, and terminates the
command in progress. The chip completes any ongoing SCSI process.
Send Asynchronous Data transfers complete immediately. Send
Synchronous Data transfers complete when the offset counter is zero.
Receive Asynchronous Data transfers complete immediately. Data left in
the FIFO should be removed by the microprocessor. Receive
Synchronous Data operations complete when all outstanding SCSI
ACK/s have been received. No extra bits are set in the
registers. The microprocessor receives the interrupt from the command
that was in progress, and the command FIFO is cleared.
Target Command Group
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
The chip is in a steady state:
Send Data – the DMA FIFO is empty
Receive Asynchronous Data – The FIFO is full (FIFO Flags
Register = 0x10), or the Transfer Counter is zero
bit 4 = 1)
Receive Synchronous Data – The Transfer Counter is zero, or the
Offset Counter is at maximum value
bit 3 = 0)
(Sequence Step
(Status
Interrupt
register
register
or
Status
5-23