LSI53CF92A LSI, LSI53CF92A Datasheet - Page 13

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

Tables
2.1
2.2
3.1
3.2
3.3
3.4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.13
5.14
5.15
5.16
6.1
6.2
6.3
6.4
Contents
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
Parity Control
Minimum Timing Requirements
Microprocessor and DMA Interface Signals
SCSI Signals
Configuration and Test Signals
Power and Ground Signals
Register Reset Values
Register Set
Transfer Rate with 40 MHz Clock (FASTCLK Bit Set)
Transfer Rate with 25 MHz Clock (FASTCLK Bit Clear)
REQ/ ACK/ Deassertion Delay Selection
REQ/ ACK/ Assertion Delay Selection
CLK Frequency vs. Clock Conversion Factor
Synchronous Transfer Rate and Minimum Clocks/Byte
DMA Modes
Command Set
Miscellaneous Commands
Disconnected State Commands
Target Selected without ATN Sequence
Target Selected with ATN Sequence (SCSI-2 Bit Not Set)
Target Selected with ATN Sequence (SCSI-2 Bit or
Queue Tag Enable Bit Set)
Initiator Select without ATN Sequence
Initiator Select with ATN Sequence
Initiator Select with ATN and Stop Sequence
Initiator Select with ATN3 Sequence
Initiator Commands
Target Commands
Target Disconnect Sequence
Target Terminate Sequence
Target Command Complete Sequence
Target Receive Command Sequence
Absolute Maximum Stress Ratings
Recommended Operating Conditions
Inputs
Outputs
2-15
4-19
4-20
4-22
4-22
4-26
4-32
4-32
5-10
5-10
5-11
5-12
5-14
5-18
5-19
5-20
5-20
5-22
2-7
3-2
3-4
3-5
3-5
4-2
4-3
5-2
5-4
5-6
5-8
5-8
5-9
6-1
6-2
6-2
6-3
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