CY8C5386LTI-005 Cypress Semiconductor Corp, CY8C5386LTI-005 Datasheet
CY8C5386LTI-005
Specifications of CY8C5386LTI-005
Related parts for CY8C5386LTI-005
CY8C5386LTI-005 Summary of contents
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... Up to four 16-bit configurable timer, counter, and PWM blocks Library of standard peripherals • 8, 16, 24, and 32-bit timers, counters, and PWMs Note 1. This feature on select devices only. See Ordering Information Cypress Semiconductor Corporation Document Number: 001-55035 Rev. *F PRELIMINARY ® PSoC 5: CY8C53 Family Data Sheet Programmable System-on-Chip (PSoC ® ...
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Content Overview 1. ARCHITECTURAL OVERVIEW ......................................... 3 2. PINOUTS ............................................................................. 5 3. PIN DESCRIPTIONS ........................................................... 9 4. CPU ................................................................................... 10 4.1 ARM Cortex-M3 CPU ............................................... 10 4.2 Cache Controller ...................................................... 12 4.3 DMA and PHUB ....................................................... 12 4.4 Interrupt Controller ...
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Architectural Overview Introducing the CY8C53 family of ultra low power, flash Programmable System-on-Chip (PSoC ® PSoC 3 and 32-bit PSoC 5 platform. The CY8C53 family provides configurable blocks of analog, digital, and interconnect circuitry around a CPU subsystem. The ...
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Figure 1-1 illustrates the major components of the CY8C53 family. They are: ARM Cortex-M3 CPU Subsystem Nonvolatile Subsystem Programming, Debug, and Test Subsystem Inputs and Outputs Clocking Power Digital Subsystem Analog Subsystem PSoC’s digital subsystem provides half of its unique ...
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SIO can be used to make the SIO function as a general purpose analog comparator. For devices with Full-Speed USB the USB physical interface is also provided (USBIO). When not using USB these pins ...
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GPIO) P2[6] (TRACEDATA[3], GPIO) P2[7] (I2C0: SCL, SIO) P12[4] (I2C0: SDA, SIO) P12[5] Vssb Vboost Vssd XRES (TMS, SWDIO, GPIO) P1[0] (TCK, SWDCK, GPIO) P1[1] (configurable XRES, GPIO) P1[2] (TDO, SWV, GPIO) P1[3] (TDI, GPIO) P1[4] (nTRST, GPIO) P1[5] ...
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GPIO) P2[5] 1 (TRACEDATA[2], GPIO) P2[6] 2 (TRACEDATA[3], GPIO) P2[7] 3 (I2C0: SCL, SIO) P12[4] 4 (I2C0: SDA, SIO) P12[5] 5 (GPIO) P6[4] 6 (GPIO) P6[5] 7 (GPIO) P6[6] 8 (GPIO) P6[7] 9 Vssb 10 Ind 11 Vboost 12 ...
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Figure 2-3 and Figure 2-4 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal analog performance on a 2-layer board. The two pins labeled Vddd must be connected together. The two pins labeled ...
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Figure 2-4. Example PCB Layout for 100-Pin TQFP Part for Optimal Analog Performance Vssd Plane 3. Pin Descriptions IDAC0, IDAC2. Low resistance output pin for high current DACs (IDAC). OpAmp0out, OpAmp2out. High current output of uncommitted [4] opamp . Extref0, ...
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Vcca. Output of analog core regulator and input to analog core. Requires a 1 µF capacitor to Vssa. Regulator output not for external use. Vccd. Output of digital core regulator and input to digital core. The two Vccd pins must ...
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The Cortex-M3 CPU subsystem includes these features: ARM Cortex-M3 CPU Programmable Nested Vectored Interrupt Controller (NVIC), tightly integrated with the CPU core Full featured debug and trace modules, tightly integrated with the CPU core Up to 128 KB of flash ...
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Table 4-2. Cortex M3 CPU Registers (continued) Register Description PRIMASK A 1-bit interrupt mask register. When set, it allows only the nonmaskable interrupt (NMI) and hard fault exception. All other exceptions and interrupts are masked. FAULTMASK A 1-bit interrupt mask ...
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Table 4-4. Priority Levels Priority Level % Bus Bandwidth 0 100.0 1 100.0 2 50.0 3 25.0 4 12.5 5 6.2 6 3.1 7 1.5 4.3.4 Transaction Modes Supported The flexible configuration of each DMA channel and the ability to ...
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Interrupt Controller The Cortex-M3 NVIC supports 16 system exceptions and 32 interrupts from peripherals, as shown in Table Table 4-5. Cortex-M3 Exceptions and Interrupts Exception Exception Type Number 1 Reset -3 (highest) 2 NMI -2 3 Hard fault -1 ...
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Table 4-6. Interrupt Vector Table (continued) Interrupt # Cortex-M3 Exception # ...
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PSoC Creator, for example). If your application requires code update through a boot loader, then use the Field Upgrade setting. Use the Unprotected setting only when no security is needed in your application. The PSoC device also ...
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Data, Address, and Control Signals PHUB Data, Address, and Control Signals Data, Address, and Control Signals Document Number: 001-55035 Rev. *F PRELIMINARY ® PSoC Figure 5-1. EMIF Block Diagram Address Signals PORTs Data Signals IO IF PORTs Control Signals PORTs ...
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Memory Map The Cortex-M3 has a fixed address map, which allows periph- erals to be accessed by simple memory access instructions. 5.6.1 Address Map The 4 GB address space is divided into the ranges shown in Table 5-2: Table ...
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System Integration 6.1 Clocking System The clocking system generates, divides, and distributes clocks throughout the PSoC system. For the majority of systems, no external crystal is required. The IMO and PLL together can generate MHz ...
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MHz 4-33 MHz IMO ECO 12-48 MHz Doubler Digital Clock Divider 16 bit Digital Clock Divider 16 bit 7 Digital Clock Divider 16 bit Digital Clock Divider 16 bit 6.1.1 Internal Oscillators 6.1.1.1 Internal Main Oscillator In most designs ...
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Firmware can reset the central timewheel. The central timewheel can be programmed to wake the system periodically and optionally issue an interrupt. This enables flexible, periodic ...
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Clock Distribution All seven clock sources are inputs to the central clock distribution system. The distribution system is designed to create multiple high precision clocks. These clocks are customized for the design’s requirements and eliminate the common problems found ...
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Power System The power system consists of separate analog, digital, and I/O supply pins, labeled Vdda, Vddd, and Vddiox, respectively. It also includes two internal 1.8 V regulators that provide the digital (Vccd) and analog (Vcca) supplies for the ...
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Table 6-2. Power Modes Power Modes Description Active Primary mode of operation, all peripherals available (program- mable) Alternate Similar to Active mode, and is Active typically configured to have fewer peripherals active to reduce power. One possible configuration is to ...
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One possible configuration is to turn off the CPU and flash, and run peripherals at full speed. 6.2.1.3 Sleep Mode Sleep mode reduces power consumption when a resume time of 15 µs is acceptable. The wake time is used ...
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Reset CY8C53 has multiple internal and external reset sources available. The reset sources are: Power source monitoring - The analog and digital power voltages, Vdda, Vddd, Vcca, and Vccd are monitored in several different modes during power up, active ...
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Other Reset Sources XRES - External Reset CY8C53 has either a single GPIO pin that is configured as an external reset or a dedicated XRES pin. Either the dedicated XRES pin or the GPIO pin, if configured, holds the ...
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Digital Input Path PRT[x]CTL PRT[x]DBL_SYNC_IN PRT[x]PS Digital System Input PICU[x]INTTYPE[y] PICU[x]INTSTAT Pin Interrupt Signal PICU[x]INTSTAT Digital Output Path PRT[x]SLW PRT[x]SYNC_OUT PRT[x]DR Digital System Output PRT[x]BYP PRT[x]DM2 PRT[x]DM1 PRT[x]DM0 Bidirectional Control PRT[x]BIE Analog Capsense Global Control CAPS[x]CFG1 PRT[x]AG Analog Global Enable ...
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Digital Input Path PRT[x]SIO_HYST_EN PRT[x]SIO_DIFF Reference Level PRT[x]DBL_SYNC_IN PRT[x]PS Digital System Input PICU[x]INTTYPE[y] PICU[x]INTSTAT Pin Interrupt Signal PICU[x]INTSTAT Digital Output Path Reference Level PRT[x]SIO_CFG PRT[x]SLW PRT[x]SYNC_OUT PRT[x]DR Digital System Output PRT[x]BYP PRT[x]DM2 PRT[x]DM1 PRT[x]DM0 Bidirectional Control PRT[x]BIE Digital Input Path ...
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Drive Modes Each GPIO and SIO pin is individually configurable into one of the eight drive modes listed in Table 6-6. Three configuration bits are used for each pin (DM[2:0]) and set in the PRTxDM[2:0] registers. Figure 6-11 depicts ...
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Pins can be used for digital input and output in these modes. Interfacing to mechanical switches is a common appli- cation for these modes. Open Drain, Drives High and Open Drain, Drives Low Open drain modes provide high impedance ...
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Vddio level or the regulated output, which is based on an internally generated reference. Typically a voltage DAC (VDAC) is used to generate the reference. The section on page 53 has more details on VDAC use and ...
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Digital Subsystem The digital programmable system creates application specific combinations of both standard and advanced digital peripherals and custom logic functions. These peripherals and logic are then interconnected to each other and to any pin on the device, providing ...
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Example Digital Components The following is a sample of the digital components available in PSoC Creator for the CY8C53 family. The exact amount of hardware resources (UDBs, routing, RAM, flash) used by a component varies with the features selected ...
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PSoC Creator automatically configures clocks and routes the I/O to the selected pins and then generates APIs to give the appli- cation complete control over the hardware. Changing the PSoC device configuration is as simple as adding a new component, ...
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Component Catalog Figure 7-3. Component Catalog The component catalog is a repository of reusable design elements that select device functionality and customize your PSoC device populated with an impressive selection of content; from simple primitives such as ...
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PSoC Creator contains all the tools necessary to complete a design, and then to maintain and extend that design for years to come. All steps of the design flow are carefully integrated and optimized for ease-of-use and to maximize productivity. ...
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Datapath Module The datapath contains an 8-bit single cycle ALU, with associated compare and condition generation logic. This datapath block is Input Muxes Input from Programmable Routing 6 PI Parallel Input/Output (to/from Programmable Routing) PO 7.2.2.6 Working Registers The ...
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Logical OR Logical XOR Pass, used to pass a value through the ALU to the shift register, mask, or another UDB register Independent of the ALU operation, these functions are available: Shift left Shift right Nibble swap Bitwise OR mask ...
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The bits of the control register, which may be written to by the system bus, are used to drive into the routing matrix, and thus provide firmware with the opportunity to control the state of UDB processing. The status register ...
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Figure 7-12. Function Mapping Example in a Bank of UDBs 8-Bit 16-Bit Quadrature Decoder Timer PWM UDB UDB UDB UDB UDB UDB 8-Bit SPI I2C Slave 12-Bit SPI UDB UDB UDB Logic ...
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I/O Port Routing There are a total of 20 DSI routes to a typical 8-bit I/O port, 16 for data and four for drive strength control. When an I/O pin is connected to the routing, there are two primary ...
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CAN Node 1 PSoC CAN Drivers CAN Controller CAN Transceiver CAN_H CAN_L 7.5.1 CAN Features CAN2.0A/B protocol implementation - ISO 11898 compliant Standard and extended frames with bytes of data per frame Message filter ...
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Tx Buffer Status TxReq Pending TxInterrupt Request (if enabled) RxMessage0 Acceptance Code 0 Rx Buffer Status RxMessage RxMessage1 Acceptance Code 1 Available RxMessage14 Acceptance Code 14 RxInterrupt RxMessage15 Acceptance Code 15 Request (if enabled) 7.6 USB PSoC includes a dedicated ...
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Timers, Counters, and PWMs The Timer/Counter/PWM peripheral is a 16-bit dedicated peripheral providing three of the most common embedded peripheral features. As almost all embedded systems use some combination of timers, counters, and PWMs. Four of them have been ...
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Flexible, configurable analog routing architecture provided by analog globals, analog mux bus, and analog local buses Successive approximation (SAR) ADC Two 8-bit DACs that provide either voltage or current output Four comparators with optional connection to configurable LUT outputs Two ...
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Analog Routing The CY8C38 family of devices has a flexible analog routing architecture that provides the capability to connect GPIOs and different analog blocks, and also route signals between different analog blocks. One of the strong points of this ...
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ExVrefL ExVrefL1 opamp0 opamp2 swinp GPIO swfol swfol P0[4] swinn GPIO P0[5] GPIO * i0 abuf_vref_int P0[6] (1.024V) GPIO i2 * P0[7] cmp0_vref (1.024V) GPIO cmp_muxvn[1:0] vref_cmp1 P4[2] cmp1_vref (0.256V) bg_vda_res_en GPIO Vdda Vdda/2 ...
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Analog local buses (abus) are routing resources located within the analog subsystem and are used to route signals between different analog blocks. There are eight abus routes in CY8C38, four in the left half (abusl [0:3]) and four in the ...
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From Analog Routing From Analog Routing 8.3.2 LUT The CY8C53 family of devices contains four LUTs. The LUT is a two input, one output lookup table that is driven by any one or two of the comparators in the chip. ...
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Opamps The CY8C53 family of devices contain two general purpose opamps. Figure 8-5. Opamp GPIO Analog Global Bus Opamp Analog Global Bus VREF Analog Internal Bus Analog Switch = GPIO The opamp is uncommitted and can be configured as ...
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PGA. The gain is switched from inverting and non inverting by changing the shared select value of the both the input muxes. The bandwidth for each gain case is listed in Table 8-2. Table ...
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Ability to invert LCD display for negative image Three LCD driver drive modes, allowing power optimization LCD driver configurable to be active when PSoC is in limited active mode Figure 8-9. LCD System LCD Global DAC Clock UDB LCD Driver ...
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Reference Source 8.9.1 Current DAC The current DAC (IDAC) can be configured for the ranges µ 256 µA, and 0 to 2.048 mA. The IDAC can be configured to source or sink current. 8.9.2 Voltage ...
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Sample and Hold The main application for a sample and hold hold a value stable while an ADC is performing a conversion. Some applica- tions require multiple signals to be sampled simultaneously, such as for power calculations ...
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JTAG Interface The IEEE 1149.1 compliant JTAG interface exists on four or five pins (the nTRST pin is optional). The JTAG clock frequency can MHz, or 1/3 of the CPU clock frequency for 8 and ...
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The Write Once Latch is a type of nonvolatile latch (NVL). The cell itself is an NVL with additional logic wrapped around it. Each WOL device contains four bytes (32 bits) of data. The wrapper outputs a ‘1’ ...
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Electrical Specifications Specifications are valid for -40°C ≤ T ≤ 85°C and Tj ≤ 100°C, except where noted. Specifications are valid for 1. 5.5 V, except A where noted. The unique flexibility of the PSoC UDBs and ...
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Device Level Specifications Specifications are valid for -40°C ≤ T ≤ 85°C and Tj ≤ 100°C, except where noted. Specifications are valid for 1. 5.5 V, except A where noted. 11.2.1 Device Level Specifications Table 11-2. DC ...
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Table 11-3. AC Specifications Parameter Description F CPU frequency CPU F Bus frequency busclk Svdd Vdd ramp rate Time from Vddd/Vdda/Vccd/Vcca ≥ Tio_init IPOR to I/O ports set to their reset states Time from Vddd/Vdda/Vccd/Vcca ≥ Tstartup PRES to ...
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Power Regulators Specifications are valid for -40°C ≤ T ≤ 85°C and Tj ≤ 100°C, except where noted. Specifications are valid for 1. 5.5 V, except A where noted. 11.3.1 Digital Core Regulator Table 11-4. Digital Core ...
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Table 11-6. Inductive Boost Regulator DC Specifications (continued) Parameter Description [9] Boost output voltage range 1.8 V 1.9 V 2.0 V 2.4 V Vboost 2.7 V 3.0 V 3.3 V 3.6 V 5.0 V Load regulation Line regulation Efficiency Table ...
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Table 11-8. GPIO DC Specifications (continued) Parameter Description [9] Cin Input capacitance Vh Input voltage hysteresis [9] (Schmitt-Trigger) Idiode Current through protection diode to Vddio and Vssio Rglobal Resistance pin to analog global bus 25°C, Vddio = 3.0 V Rmux ...
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Table 11-10. SIO DC Specifications (continued) Parameter Description Output voltage low Vol Rpullup Pull up resistor Rpulldown Pull down resistor Iil Input leakage current (absolute [9] value) Vih < Vddsio Vih > Vddsio [9] Cin Input Capacitance Input voltage hysteresis ...
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USBIO For operation in USB mode, Vddd range condition is 3.15 V ≤ Vddd ≤ 3.45 V (USB regulator bypassed) or 4.35 V ≤ Vddd ≤ 5.25 V (USB regulator in use). For operation in GPIO mode, the standard ...
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Table 11-14. USB Driver AC Specifications Parameter Description Tr Transition rise time Tf Transition fall time TR Rise/fall time matching Vcrs Output signal crossover voltage 11.4.4 XRES Table 11-15. XRES DC Specifications Parameter Description Vih Input voltage high threshold Vil ...
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Analog Peripherals Specifications are valid for -40°C ≤ T ≤ 85°C and Tj ≤ 100°C, except where noted. Specifications are valid for 1. 5.5 V, except A where noted. 11.5.1 Opamp Table 11-17. Opamp DC Specifications Parameter ...
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SAR ADC Table 11-20. SAR ADC DC Specifications Parameter Description Resolution Number of channels - single ended Number of channels - differential [9] Monotonicity Gain error Input offset voltage Current consumption Input voltage range - single ended Input voltage ...
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Comparator Table 11-23. Comparator DC Specifications Parameter Description Input offset voltage in fast mode Vioff Input offset voltage in slow mode Input offset voltage in fast mode Vioff Input offset voltage in slow mode Vioff Input offset voltage in ...
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IDAC Table 11-25. IDAC (Current Digital-to-Analog Converter) DC Specifications Parameter Description Resolution Iout Output current [9] High [9] Medium [9] Low INL Integral non linearity DNL Differential non linearity Ezs Zero scale error Eg Gain error IDAC_ICC DAC current ...
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Table 11-28. VDAC (Voltage Digital-to-Analog Converter) AC Specifications Parameter Description [9] Update rate Fdac [9] Update rate [9] Settling time to 0.5LSB [9] Tsettle High [9] Low 11.5.8 Discrete Time Mixer The discrete time mixer is used for modulating (shifting ...
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Transimpedance Amplifier The TIA is created using a SC/CT Analog Block, see the TIA component data sheet in PSoC Creator for full AC/DC specifications, and APIs and example code. Table 11-33. Transimpedance Amplifier (TIA) DC Specifications Parameter Description Vioff ...
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Programmable Gain Amplifier The PGA is created using a SC/CT Analog Block, see the PGA component data sheet in PSoC Creator for full AC/DC specifications, and APIs and example code. Table 11-35. PGA DC Specifications Parameter Description [9] Vos ...
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Unity Gain Buffer The Unity Gain Buffer is created using a SC/CT Analog Block. See the Unity Gain Buffer component data sheet in PSoC Creator for full AC/DC specifications, and APIs and example code. Table 11-37. Unity Gain Buffer ...
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Table 11-40. LCD Direct Drive DC Specifications (continued) Parameter Description Static (1 common) Icc LCD system operating current LCD Icc LCD system operating current LCD 1/4 duty (4 commons) Icc LCD system operating current LCD Icc LCD system operating current ...
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Digital Peripherals Specifications are valid for -40°C ≤ T ≤ 85°C and Tj ≤ 100°C, except where noted. Specifications are valid for 1. 5.5 V, except A where noted. 11.6.1 Timer Table 11-42. Timer DC Specifications Parameter ...
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Table 11-45. Counter AC Specifications (continued) Parameter Description Reset pulse width Reset pulse width (external) 11.6.3 Pulse Width Modulation Table 11-46. PWM DC Specifications Parameter Description Block current consumption 3 MHz 12 MHz 48 MHz 67 MHz 80 MHz Table ...
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Controller Area Network Table 11-50. CAN DC Specifications Parameter Description Block current consumption Table 11-51. CAN AC Specifications Parameter Description Bit rate 11.6.6 USB Table 11-52. USB DC Specifications Parameter Description Operating current 11.6.7 Universal Digital Blocks (UDBs) ...
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Memory Specifications are valid for -40°C ≤ T ≤ 85°C and Tj ≤ 100°C, except where noted. Specifications are valid for 1. 5.5 V, except A where noted. 11.7.1 Flash Table 11-54. Flash DC Specifications Parameter Description ...
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Table 11-57. EEPROM AC Specifications Parameter Description Twrite Single byte erase/write cycle time EEPROM endurance EEPROM data retention time 11.7.3 Nonvolatile Latches (NVL) Table 11-58. NVL DC Specifications Parameter Description Erase and program voltage Table 11-59. NVL AC Specifications Parameter ...
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External Memory Interface EM_CEn Taddrv EM_Addr Toev EM_OEn EM_WEn EM_Data Table 11-62. Asynchronous Read Cycle Specifications Parameter Description T EMIF Clock period Tcel EM_CEn low time Taddrv EM_CEn low to EM_Addr valid Taddrh Address hold time after EM_OEn high ...
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Taddrv EM_ Addr EM_ CEn EM_ OEn Twev Tdcev EM_ Data Table 11-63. Asynchronous Write Cycle Specifications Parameter Description T EMIF Clock period Taddrv EM_CEn low to EM_Addr valid Taddrh Address hold time after EM_WEn high Tcel EM_CEn low time ...
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Tcp EM_ Clock Tceld EM_ CEn Taddrv EM_ Addr Toeld EM_ OEn EM_ Data Tadscld EM_ ADSCn Table 11-64. Synchronous Read Cycle Specifications Parameter Description T EMIF Clock period Tcp EM_Clock Period Tceld EM_Clock low to EM_CEn low Tcehd EM_Clock ...
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Tcp EM_ Clock Tceld EM_ CEn Taddrv EM_ Addr Tweld EM_ WEn Tds EM_ Data Tadscld EM_ ADSCn Table 11-65. Synchronous Write Cycle Specifications Parameter Description T EMIF Clock period Tcp EM_Clock Period Tceld EM_Clock low to EM_CEn low Tcehd ...
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PSoC System Resources Specifications are valid for -40°C ≤ T ≤ 85°C and Tj ≤ 100°C, except where noted. Specifications are valid for 1. 5.5 V, except A where noted. 11.8.1 POR with Brown Out For brown ...
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Interrupt Controller Table 11-70. Interrupt Controller AC Specifications Parameter Description Delay from Interrupt signal input to ISR code execution from main line code Delay from Interrupt signal input to ISR code execution from ISR code 11.8.4 JTAG Interface Table ...
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Clocking Specifications are valid for -40°C ≤ T ≤ 85°C and Tj ≤ 100°C, except where noted. Specifications are valid for 1. 5.5 V, except A where noted. 11.9.1 32 kHz External Crystal Table 11-74. 32 kHz ...
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Table 11-77. IMO AC Specifications (continued) Parameter Description [9] Jitter (peak to peak) Jp MHz MHz [9] Jitter (long term) Jperiod MHz MHz 11.9.3 Internal Low Speed Oscillator ...
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Phase-Locked Loop Table 11-82. PLL DC Specifications Parameter Description Idd PLL operating current Table 11-83. PLL AC Specifications Parameter Description [21] Fpllin PLL input frequency PLL intermediate frequency [21] Fpllout PLL output frequency Lock time at startup [9] Jperiod-rms ...
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... SAR 2 ✔ CY8C5385LTI-104 1x12-bit SAR 2 ✔ CY8C5385AXI-025 1x12-bit SAR 2 ✔ CY8C5385AXI-096 1x12-bit SAR Flash ✔ CY8C5386AXI-076 1x12-bit SAR 2 ✔ CY8C5386LTI-005 1x12-bit SAR 2 ✔ CY8C5386AXI-001 1x12-bit SAR 2 ✔ CY8C5386LTI-053 1x12-bit SAR 2 ✔ CY8C5386AXI-081 1x12-bit SAR 2 ✔ CY8C5386AXI-105 1x12-bit SAR 2 128 KB Flash ✔ ...
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Part Numbering Conventions PSoC 5 devices follow the part numbering convention described below. All fields are single character alphanumeric ( … …, Z) unless stated otherwise. CY8Cabcdefg-xxx a: Architecture 3: PSoC 3 5: PSoC ...
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Packaging Table 13-1. Package Characteristics Parameter Description T Operating ambient temperature A Tj Operating junction temperature Package θ JA (68 QFN) Tja Package θ JA (100 TQFP) Tja Package θ JC (68 QFN) Tjc Package θ JC (100 TQFP) ...
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Figure 13-2. 100-Pin TQFP ( 1.4 mm) Package Outline 16.00±0.25 SQ 14.00±0.05 SQ 100 SEATING PLANE 1.60 MAX. 0.08 0.20 MAX. Document Number: 001-55035 Rev. *F PRELIMINARY ® PSoC 5: CY8C53 Family Data Sheet ...
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Revision History ® Description Title: PSoC 5: CY8C53 Family Data Sheet Programmable System-on-Chip (PSoC Document Number: 001-55035 Submission Rev. ECN No. Date ** 2759055 09/02/09 *A 2824626 12/09/09 *B 2873520 02/04/10 Document Number: 001-55035 Rev. *F PRELIMINARY ® PSoC ...
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Description Title: PSoC 5: CY8C53 Family Data Sheet Programmable System-on-Chip (PSoC Document Number: 001-55035 *C 2911720 04/13/10 Document Number: 001-55035 Rev. *F PRELIMINARY ® PSoC 5: CY8C53 Family Data Sheet MKEA Updated Vb pin in PCB Schematic. Updated Tstartup ...
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Description Title: PSoC 5: CY8C53 Family Data Sheet Programmable System-on-Chip (PSoC Document Number: 001-55035 *D 2936486 05/24/10 *E 2944841 6/4/2010 *F 2960407 06/24/10 Document Number: 001-55035 Rev. *F PRELIMINARY ® PSoC 5: CY8C53 Family Data Sheet MKEA Replaced Vddio ...
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... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...