MC9S08AW60CFGE Freescale, MC9S08AW60CFGE Datasheet - Page 86

• Manufacturer Part Number: MC9S08AW60CFGE
• Manufacturer: Freescale

Specifications of MC9S08AW60CFGE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 34
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

Chapter 6 Parallel Input/Output
Refer to
port E pins as SCI pins.
Refer to
pins as SPI pins.
Refer to
channel pins.
6.3.6
Port F pins are general-purpose I/O pins. Parallel I/O function is controlled by the port F data (PTFD) and
data direction (PTFDD) registers which are located in page zero register space. The pin control registers,
pullup enable (PTFPE), slew rate control (PTFSE), and drive strength select (PTFDS) are located in the
high page registers. Refer to
general-purpose I/O control and
Port F general-purpose I/O is shared with TPM1 and TPM2 timer channels. When any of these shared
functions is enabled, the direction, input or output, is controlled by the shared function and not by the data
direction register of the parallel I/O port. Also, for pins which are configured as outputs by the shared
function, the output data is controlled by the shared function and not by the port data register.
Refer to
channel pins.
6.3.7
Port G pins are general-purpose I/O pins. Parallel I/O function is controlled by the port G data (PTGD) and
data direction (PTGDD) registers which are located in page zero register space. The pin control registers,
pullup enable (PTGPE), slew rate control (PTGSE), and drive strength select (PTGDS) are located in the
high page registers. Refer to
general-purpose I/O control and
Port G general-purpose I/O is shared with KBI, XTAL, and EXTAL. When a pin is enabled as a KBI input,
the pin functions as an input regardless of the state of the associated PTG data direction register bit. When
the external oscillator is enabled, PTG5 and PTG6 function as oscillator pins. In this case the associated
parallel I/O and pin control registers have no control of the pins.
86
Port F
Port G
Chapter 11, “Serial Communications Interface
Chapter 12, “Serial Peripheral Interface
Chapter 10, “Timer/PWM
Chapter 10, “Timer/PWM
Port F
Port G
MCU Pin:
MCU Pin:
Bit 7
R
Section 6.4, “Parallel I/O
Section 6.4, “Parallel I/O
Bit 7
0
Section 6.5, “Pin
Section 6.5, “Pin
PTF6
MC9S08AC16 Series Data Sheet, Rev. 8
(S08TPMV3)”
(S08TPMV3)” for more information about using port F pins as TPM
EXTAL
6
PTG6/
Figure 6-8. Port G Pin Names
Figure 6-7. Port F Pin Names
6
TPM2CH1
PTF5/
PTG5/
XTAL
5
5
(S08SPIV3)”
Control” for more information about pin control.
Control” for more information about pin control.
for more information about using port E pins as TPM
TPM2CH0
Control” for more information about
Control” for more information about
PTF4/
PTG4/
KBIP4
(S08SCIV4)”
4
4
for more information about using port E
PTG3/
KBIP3
3
R
3
for more information about using
PTG2/
KBIP2
2
R
2
PTG1/
KBIP1
TPM1CH3
Freescale Semiconductor
1
PTF1/
1
PTG0/
KBIP0
Bit 0
TPM1CH2
PTF0/
Bit 0