MC9S08AW32CFGE Freescale, MC9S08AW32CFGE Datasheet
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... MC9S08AW60 MC9S08AW48 MC9S08AW32 MC9S08AW16 Data Sheet HCS08 Microcontrollers MC9S08AW60 Rev 2 12/2006 freescale.com ...
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MC9S08AW60 Features 8-Bit HCS08 Central Processor Unit (CPU) • 40-MHz HCS08 CPU (central processor unit) • 20-MHz internal bus frequency • HC08 instruction set with added BGND instruction • Single-wire background debug mode interface • Breakpoint capability to allow single ...
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MC9S08AW60 Data Sheet Covers: MC9S08AW60 MC9S08AW48 MC9S08AW32 MC9S08AW16 MC9S08AW60 Rev 2 12/2006 ...
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... IDD issues, added RTI figure, bandgap information, and incorporated electricals edits and any ProjectSync issues. This product incorporates SuperFlash Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2006. All rights reserved. Description of Changes ® ...
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... Serial Peripheral Interface (S08SPIV3) ........................................ 199 Chapter 13 Inter-Integrated Circuit (S08IICV1) ............................................... 215 Chapter 14 Analog-to-Digital Converter (S08ADC10V1)................................ 233 Chapter 15 Development Support ................................................................... 261 Appendix A Electrical Characteristics and Timing Specifications ................ 283 Appendix B Ordering Information and Mechanical Drawings........................ 309 Freescale Semiconductor List of Chapters Title MC9S08AW60 Data Sheet, Rev 2 Page 7 ...
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... LVD Enabled in Stop Mode ...........................................................................................37 3.6.5 On-Chip Peripheral Modules in Stop Modes .................................................................37 4.1 MC9S08AW60 Series Memory Map ..............................................................................................39 4.1.1 Reset and Interrupt Vector Assignments ........................................................................42 4.2 Register Addresses and Bit Assignments ........................................................................................43 4.3 RAM ................................................................................................................................................49 Freescale Semiconductor Contents Title Chapter 1 Introduction Chapter 2 Pins and Connections , .........................................................................28 SS DDAD ...
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... System Background Debug Force Reset Register (SBDFR) ..........................................75 5.9.4 System Options Register (SOPT) ...................................................................................75 5.9.5 System MCLK Control Register (SMCLK) ...................................................................76 5.9.6 System Device Identification Register (SDIDH, SDIDL) ..............................................77 5.9.7 System Real-Time Interrupt Status and Control Register (SRTISC) .............................78 10 Title Chapter 5 MC9S08AW60 Data Sheet, Rev 2 Page Freescale Semiconductor ...
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... Port G I/O Registers (PTGD and PTGDD) ..................................................................106 6.7.14 Port G Pin Control Registers (PTGPE, PTGSE, PTGDS) ...........................................107 Central Processor Unit (S08CPUV2) 7.1 Introduction ...................................................................................................................................109 7.1.1 Features .........................................................................................................................109 7.2 Programmer’s Model and CPU Registers .....................................................................................110 Freescale Semiconductor Title Chapter 6 Parallel Input/Output Chapter 7 MC9S08AW60 Data Sheet, Rev 2 Page 11 ...
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... ICG Filter Registers (ICGFLTU, ICGFLTL) ...............................................................139 8.3.6 ICG Trim Register (ICGTRM) .....................................................................................140 8.4 Functional Description ..................................................................................................................140 8.4.1 Off Mode (Off) .............................................................................................................141 8.4.2 Self-Clocked Mode (SCM) ...........................................................................................141 8.4.3 FLL Engaged, Internal Clock (FEI) Mode ...................................................................142 12 Title Chapter 8 MC9S08AW60 Data Sheet, Rev 2 Page Freescale Semiconductor ...
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... TPMxCHn — TPMx Channel n I/O Pins .....................................................................169 10.4 Register Definition ........................................................................................................................169 10.4.1 Timer x Status and Control Register (TPMxSC) ..........................................................170 10.4.2 Timer x Counter Registers (TPMxCNTH:TPMxCNTL) .............................................171 Freescale Semiconductor Title Chapter 9 Keyboard Interrupt (S08KBIV1) Chapter 10 Timer/PWM (S08TPMV2) MC9S08AW60 Data Sheet, Rev 2 Page ...
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... Block Diagrams ............................................................................................................201 12.0.3 SPI Baud Rate Generation ............................................................................................203 12.1 External Signal Description ..........................................................................................................204 12.1.1 SPSCK — SPI Serial Clock .........................................................................................204 12.1.2 MOSI — Master Data Out, Slave Data In ....................................................................204 14 Title Chapter 11 Chapter 12 MC9S08AW60 Data Sheet, Rev 2 Page Freescale Semiconductor ...
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... Functional Description ..................................................................................................................225 13.4.1 IIC Protocol ..................................................................................................................225 13.5 Resets ............................................................................................................................................228 13.6 Interrupts .......................................................................................................................................228 13.6.1 Byte Transfer Interrupt .................................................................................................229 13.6.2 Address Detect Interrupt ...............................................................................................229 13.6.3 Arbitration Lost Interrupt .............................................................................................229 13.7 Initialization/Application Information ..........................................................................................230 Freescale Semiconductor Title Chapter 13 MC9S08AW60 Data Sheet, Rev 2 Page 15 ...
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... Initialization Information ..............................................................................................................253 14.6.1 ADC Module Initialization Example ...........................................................................253 14.7 Application Information ................................................................................................................255 14.7.1 External Pins and Routing ............................................................................................255 14.7.2 Sources of Error ............................................................................................................257 16 Title Chapter 14 ) ................................................................................................239 DDAD ) ..............................................................................................239 SSAD ) .................................................................................239 REFH ) ..................................................................................239 REFL MC9S08AW60 Data Sheet, Rev 2 Page Freescale Semiconductor ...
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... A.10.1 Control Timing ..............................................................................................................300 A.10.2 Timer/PWM (TPM) Module Timing.............................................................................302 A.11 SPI Characteristics .........................................................................................................................303 A.12 FLASH Specifications....................................................................................................................306 A.13 EMC Performance..........................................................................................................................307 A.13.1 Radiated Emissions .......................................................................................................307 A.13.2 Conducted Transient Susceptibility...............................................................................307 Freescale Semiconductor Title Chapter 15 Development Support Appendix A MC9S08AW60 Data Sheet, Rev 2 Page ...
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... Ordering Information and Mechanical Drawings B.1 Ordering Information .....................................................................................................................309 B.2 Orderable Part Numbering System ................................................................................................310 B.2.1 Consumer and Industrial Orderable Part Numbering System .......................................310 B.2.2 Automotive Orderable Part Numbering System............................................................310 B.3 Mechanical Drawings.....................................................................................................................310 18 Title Appendix B MC9S08AW60 Data Sheet, Rev 2 Page Freescale Semiconductor ...
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... SCI1 SCI2 SPI1 TPM1 TPM1CLK TPM2 TPM2CLK I/O pins 1.2 MCU Block Diagrams The block diagram shows the structure of the MC9S08AW60 Series. Freescale Semiconductor for memory sizes and package types. FLASH RAM 63,280 49,152 2048 32,768 16,384 1024 Package Options 64-pin ...
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... PTB0/AD1P0 PTC6 PTC5/RxD2 PTC4 PTC3/TxD2 PTC2/MCLK PTC1/SDA1 PTC0/SCL1 8 PTD7/AD1P15/KBI1P7 PTD6/AD1P14/TPM1CLK PTD5/AD1P13 PTD4/AD1P12/TPM2CLK PTD3/AD1P11/KBI1P6 PTD2/AD1P10/KBI1P5 PTD1/AD1P9 PTD0/AD1P8 PTE7/SPSCK1 PTE6/MOSI1 PTE5/MISO1 PTE4/SS1 PTE3/TPM1CH1 PTE2/TPM1CH0 6 PTE1/RxD1 PTE0/TxD1 PTF7 PTF6 PTF5/TPM2CH1 PTF4/TPM2CH0 2 PTF3/TPM1CH5 3 PTF2/TPM1CH4 PTF1/TPM1CH3 PTF0/TPM1CH2 5 PTG6/EXTAL PTG5/XTAL PTG4/KBI1P4 PTG3/KBI1P3 PTG2/KBI1P2 PTG1/KBI1P1 . DD PTG0/KBI1P0 Freescale Semiconductor ...
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... Some of the modules inside the MCU have clock source choices. connection diagram. The ICG supplies the clock sources: • ICGOUT is an output of the ICG module one of the following: — The external crystal oscillator — An external clock source Freescale Semiconductor Table 1-3. Versions of On-Chip Modules Module (S08ADC10) (S08ICG) (S08IIC) ...
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... ICGLCLK — Development tools can select this internal self-clocked source (~ 8 MHz) to speed up BDC communications in systems where the bus clock is slow. • ICGERCLK — External reference clock can be selected as the real-time interrupt clock source. Can also be used as the ALTCLK input to the ADC module. 22 MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor ...
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... Chapter 2 Pins and Connections 2.1 Introduction This chapter describes signals that connect to package pins. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. Freescale Semiconductor MC9S08AW60 Data Sheet, Rev 2 23 ...
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... PTF6 12 PTE0/TxD1 13 PTE1/RxD1 14 PTE2/TPM1CH0 15 PTE3/TPM1CH1 Figure 2-1. MC9S08AW60 Series in 64-Pin QFP/LQFP Package 64-Pin QFP 64-Pin LQFP MC9S08AW60 Data Sheet, Rev PTG3/KBI1P3 47 PTD3/KBI1P6/AD1P11 46 PTD2/KBI1P5/AD1P10 45 V SSAD 44 V DDAD 43 PTD1/AD1P9 42 PTD0/AD1P8 41 PTB7/AD1P7 40 PTB6/AD1P6 39 PTB5/AD1P5 38 PTB4/AD1P4 37 PTB3/AD1P3 PTB2/AD1P2 36 35 PTB1/AD1P1 34 PTB0/AD1P0 PTA7 Freescale Semiconductor ...
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... RESET PTF0/TPM1CH2 4 5 PTF1/TPM1CH3 6 PTF4/TPM2CH0 7 PTF5/TPM2CH1 8 PTF6 PTE0/TxD1 9 10 PTE1/RxD1 PTE2/TPM1CH0 11 12 PTE3/TPM1CH1 Figure 2-2. MC9S08AW60 Series in 48-Pin QFN Package Freescale Semiconductor 48-Pin QFN MC9S08AW60 Data Sheet, Rev 2 Chapter 2 Pins and Connections 36 PTG3/KBI1P3 35 PTD3/KBI1P6/AD1P11 34 PTD2/KBI1P5/AD1P10 33 V SSAD 32 V DDAD 31 PTD1/AD1P9 30 PTD0/AD1P8 ...
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... Figure 2-3. MC9S08AW60 Series in 44-Pin LQFP Package 2.3 Recommended System Connections Figure 2-4 shows pin connections that are common to almost all MC9S08AW60 Series application systems 44-Pin LQFP MC9S08AW60 Data Sheet, Rev PTG3/KBI1P3 33 32 PTD3/KBI1P6/AD1P11 31 PTD2/KBI1P5/AD1P10 30 V SSAD 29 V DDAD 28 PTD1/AD1P9 PTD0/AD1P8 27 PTB3/AD1P3 26 PTB2/AD1P2 25 PTB1/AD1P1 24 PTB0/AD1P0 Freescale Semiconductor ...
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... Not required if PTF0/TPM1CH2 using the internal PTF1/TPM1CH3 clock option. 2. These are the PTF2/TPM1CH4 same pins as PTF3/TPM1CH5 PTG5 and PTG6 PTF4/TPM2CH0 3. RC filters on PTF5/TPM2CH1 RESET and IRQ are recommended for EMC-sensitive applications. Freescale Semiconductor V REFH MC9S08AW60 V DDAD C BYAD 0.1 μF V SSAD V REFL 0.1 μ ...
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... C1 and C2 which are usually the same size first-order approximation, use estimate of combined pin and PCB capacitance for each oscillator pin (EXTAL and XTAL DDAD SSAD (S08ICGV4).” (when used) and R S MC9S08AW60 Data Sheet, Rev 2 and pin. This SS pin through a low-impedance SS ) equivalent to Self_reset should be low-inductance F Freescale Semiconductor ...
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... External Interrupt Pin (IRQ) The IRQ pin is the input source for the IRQ interrupt and is also the input for the BIH and BIL instructions. If the IRQ function is not enabled, this pin does not perform any function. Freescale Semiconductor , V ) REFH REFL ...
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... Chapter 9, “Keyboard Interrupt (S08KBIV1)” Chapter 14, “Analog-to-Digital Converter (S08ADC10V1)” Chapter 12, “Serial Peripheral Interface (S08SPIV3)” Chapter 10, “Timer/PWM (S08TPMV2)” Chapter 11, “Serial Communications Interface (S08SCIV2)” Chapter 10, “Timer/PWM (S08TPMV2)” MC9S08AW60 Data Sheet, Rev 2 Figure 2-4 for Chapter 6, “Parallel 1 Reference Freescale Semiconductor ...
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... Selecting a higher priority pin function with a lower priority function already enabled can cause spurious edges to the lower priority module recommended that all modules that share a pin be disabled before enabling another module. Freescale Semiconductor Table 2-1. Pin Sharing Priority Alternate Function Chapter 10, “Timer/PWM (S08TPMV2)” ...
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... Chapter 2 Pins and Connections 32 MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor ...
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... When the BKGD/MS pin is low at the rising edge of reset • When a BACKGROUND command is received through the BKGD pin • When a BGND instruction is executed • When encountering a BDC breakpoint • When encountering a DBG breakpoint Freescale Semiconductor MC9S08AW60 Data Sheet, Rev 2 33 ...
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... MCU is operated in run mode for the first time. When the MC9S08AW60 Series is shipped from the Freescale Semiconductor factory, the FLASH program memory is erased by default unless specifically noted so there is no program that could be executed in run mode until the FLASH memory is initially programmed ...
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... Upon wake-up from stop2 mode, the MCU will start up as from a power-on reset (POR) except pin states remain latched. The CPU will take the reset vector. The system and all peripherals will be in their default reset states and must be initialized. Freescale Semiconductor Table 3-1. Stop Mode Behavior RAM ...
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... ENBDM bit is set. After entering background debug mode, all background commands are available. Table 3-2 background debug mode is enabled. 36 Support” of this data sheet. If ENBDM is set when summarizes the behavior of the MCU in stop when entry into the MC9S08AW60 Data Sheet, Rev 2 Table 3-1. The Freescale Semiconductor ...
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... Refer to Mode,” and Section 3.6.2, “Stop3 Peripheral CPU RAM FLASH Parallel Port Registers ADC1 ICG IIC Freescale Semiconductor RAM ICG ADC1 Standby Active Optionally on Table 3-3 summarizes the behavior of the MCU in stop when the RAM ICG ...
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... OSCSTEN = 1). 38 Table 3-4. Stop Mode Behavior (continued) Stop2 Off 4 Optionally On Off Off Off Standby States Held MC9S08AW60 Data Sheet, Rev 2 Mode Stop3 3 Optionally On 4 Optionally On Standby Standby Standby Standby States Held Freescale Semiconductor ...
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... MC9S08AW60 Series of MCUs consists of RAM, FLASH program memory for nonvolatile data storage, plus I/O and control/status registers. The registers are divided into three groups: • Direct-page registers ($0000 through $006F) • High-page registers ($1800 through $185F) • Nonvolatile registers ($FFB0 through $FFBF) Freescale Semiconductor MC9S08AW60 Data Sheet, Rev 2 Figure 4-2 shows 39 ...
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... RAM 2048 BYTES $086F $0870 FLASH 3984 BYTES $17FF $1800 $185F $1860 $3FFF $4000 FLASH $FFFF MC9S08AW60 Data Sheet, Rev 2 DIRECT PAGE REGISTERS RAM 2048 BYTES RESERVED 3984 BYTES HIGH PAGE REGISTERS RESERVED 10,144 BYTES FLASH 49,152 BYTES MC9S08AW48 Freescale Semiconductor ...
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... HIGH PAGE REGISTERS $185F $1860 RESERVED 26,528 BYTES $7FFF $8000 FLASH 32,768 BYTES $FFFF MC9S08AW32 Figure 4-2. MC9S08AW32 and MC9S08AW16 Memory Map Freescale Semiconductor $0000 DIRECT PAGE REGISTERS $006F $0070 1024 BYTES $046F $0470 RESERVED 5008 BYTES $17FF $1800 HIGH PAGE REGISTERS ...
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... Figure 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the Freescale-provided equate file for the MC9S08AW60 Series. For more details about resets, interrupts, interrupt priority, and local interrupt mask controls, refer to Interrupts, and System Confi ...
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... Cells that are not associated with named bits are shaded. A shaded cell with a 0 indicates this unused bit always reads Shaded cells with dashes indicate unused or reserved bit locations that could read 0s. Freescale Semiconductor can use the more efficient direct addressing mode which only and Table 4-4 the whole address in column one is shown in bold ...
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... IRQF IRQACK IRQIE IRQMOD — — — KBF KBACK KBIE KBIMOD KBIPE2 KBIPE1 KBIPE0 CLKSA PS2 PS1 ELS0B ELS0A Freescale Semiconductor Bit 0 — — R — — — PS0 Bit 8 Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 ...
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... SCI2S1 TDRE $0045 SCI2S2 0 $0046 SCI2C3 R8 $0047 SCI2D Bit 7 $0048 ICGC1 HGO $0049 ICGC2 LOLRE $004A ICGS1 $004B ICGS2 0 $004C ICGFLTU 0 $004D ICGFLTL $004E ICGTRM $004F Reserved — Freescale Semiconductor CH1IE MS1B MS1A CH2IE MS2B MS2A CH3IE MS3B MS3A CH4IE MS4B ...
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... CLKSA PS2 PS1 ELS0B ELS0A ELS1B ELS1A — — — — — — Freescale Semiconductor Bit 0 LSBFE SPC0 SPR0 0 0 Bit 0 — — RXAK — — PS0 Bit 8 Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 — — ...
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... PTAPE PTAPE7 $1841 PTASE PTASE7 $1842 PTADS PTADS7 $1843 Reserved — $1844 PTBPE PTBPE7 $1845 PTBSE PTBSE7 Freescale Semiconductor 4-3, are accessed much less often than other I/O and control registers PIN COP ILOP COPT STOPE — MPE — — ...
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... PTESE1 PTESE0 PTEDS2 PTEDS1 PTEDS0 — — — — PTFPE2 PTFPE1 PTFPE0 PTFSE2 PTFSE1 PTFSE0 PTFDS2 PTFDS1 PTFDS0 — — — — PTGPE2 PTGPE1 PTGPE0 PTGSE2 PTGSE1 PTGSE0 PTGDS2 PTGDS1 PTGDS0 — — — — — — — — Freescale Semiconductor ...
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... MC9S08AW60 Series usually best to re-initialize the stack pointer to the top of the RAM so the direct page RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the highest address of the RAM in the Freescale-provided equate file). LDHX #RamLast+1 ...
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... FLASH erase and programming operations, in-application programming is also possible through other software-controlled communication paths. For a more detailed discussion of in-circuit and in-application programming, refer to the HCS08 Family Reference Manual, Volume I, Freescale Semiconductor document order number HCS08RMv1/D. 50 Section 4.5, MC9S08AW60 Data Sheet, Rev 2 “ ...
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... Excluding start/end overhead 2 Because the page and mass erase times can be longer than the COP watchdog timeout, the COP should be serviced during any software erase routine. Freescale Semiconductor (FCDIV)”). This register can be written only ) is used by the command processor to time FCLK ...
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... The command sequence must be completed by clearing FCBEF to launch the command. burst programming. The FCDIV register must be initialized before using any FLASH commands. This only must be done once following a reset. 52 NOTE Figure 4 flowchart for executing all of the commands except for MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor ...
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... The next sequential address selects a byte on the same physical row as the current byte being programmed. A row of FLASH memory consists of 64 bytes. A byte within a row is selected by addresses A5 through A0. A new row begins when addresses A5 through A0 are all zero. Freescale Semiconductor (Note 1) Note 1: Required only once after reset. ...
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... WRITE COMMAND ($25) TO FCMD WRITE 1 TO FCBEF Note 2: Wait at least four bus cycles before TO LAUNCH COMMAND (Note 2) AND CLEAR FCBEF YES FPVIO OR FACCERR ? NO YES NEW BURST COMMAND ? NO 0 FCCF ? 1 DONE MC9S08AW60 Data Sheet, Rev 2 checking FCBEF or FCCF. ERROR EXIT Freescale Semiconductor ...
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... For example, in order to protect the last 8192 bytes of memory (addresses $E000 through $FFFF), the FPS bits must be set to 1101 111 which results in the value $DFFF as the last address of unprotected memory. In addition to programming the FPS bits to the appropriate value, FPDIS (bit 0 of NVPROT) must Freescale Semiconductor NVPROT)”). MC9S08AW60 Data Sheet, Rev 2 Chapter 4 Memory Section 4 ...
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... NVOPT location which can be done at the same time the FLASH memory is programmed. The 1:0 state disengages security and the other three combinations engage security. Notice the erased state (1:1) makes 56 1 A12 A11 A10 A9 A8 Figure 4-5. Block Protection Mechanism MC9S08AW60 Data Sheet, Rev Freescale Semiconductor ...
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... Mass erase FLASH if necessary. 3. Blank check FLASH. Provided FLASH is completely erased, security is disengaged until the next reset. To avoid returning to secure mode after the next reset, program NVOPT so SEC01:SEC00 = 1:0. Freescale Semiconductor MC9S08AW60 Data Sheet, Rev 2 Chapter 4 Memory 57 ...
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... There is also an 8-byte comparison key in FLASH memory. Refer to Table 4-4 for the absolute address assignments for all FLASH registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file normally is used to translate these names into the appropriate absolute addresses. 4.6.1 FLASH Clock Divider Register (FCDIV) Bit 7 of this register is a read-only status fl ...
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... MCU is secure, the contents of RAM and FLASH memory cannot be accessed by instructions from any unsecured source including the background debug interface. For more detailed information about security, refer to Section 4.5, “Security.” Freescale Semiconductor Table 4-7. FLASH Clock Divider Settings DIV5:DIV0 (Decimal) 12 ...
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... Writes to $FFB0–$FFB7 are interpreted as the start of a FLASH programming or erase command. 1 Writes to NVBACKKEY ($FFB0–$FFB7) are interpreted as comparison key writes. 60 Table 4-9. Security States Description 0:0 0:1 1:0 unsecured 1 KEYACC Description Section 4.5, MC9S08AW60 Data Sheet, Rev 2 secure secure secure “Security.” Freescale Semiconductor ...
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... Bits 3, 1, and 0 always read 0 and writes have no meaning or effect. The remaining five bits are status bits that can be read at any time. Writes to these bits have special meanings that are discussed in the bit descriptions FCCF FCBEF W Reset Unimplemented or Reserved Freescale Semiconductor 5 4 FPS5 FPS4 FPS3 (1) (1) Description 5 4 FPVIOL FACCERR ...
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... After a blank check command is completed and FCCF = 1, FBLANK = 0 indicates the FLASH array is not completely erased. 1 After a blank check command is completed and FCCF = 1, FBLANK = 1 indicates the FLASH array is completely erased (all $FF). 62 Description Section 4.4.5, “Access MC9S08AW60 Data Sheet, Rev 2 Errors.” FACCERR is cleared by Freescale Semiconductor ...
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... Mass erase (all FLASH) All other command codes are illegal and generate an access error not necessary to perform a blank check command after a mass erase operation. Only blank check is required as part of the security unlocking mechanism. Freescale Semiconductor Execution” for a detailed discussion of FLASH 5 4 ...
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... Chapter 4 Memory 64 MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor ...
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... SP is forced to $00FF at reset. The MC9S08AW60 Series has seven sources for reset: • Power-on reset (POR) • Low-voltage detect (LVD) • Computer operating properly (COP) timer Freescale Semiconductor MC9S08AW60 Data Sheet, Rev 2 Table 5-10) 65 ...
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... If an event occurs in an enabled interrupt source, an associated read-only status flag will become set. The CPU will not respond until and unless the local interrupt enable is a logic 1 to enable the interrupt. The 66 selected. The reset pin is driven low for 34 Self_reset Section 5.9.4, “System Options Register MC9S08AW60 Data Sheet, Rev 2 (SOPT)” for Freescale Semiconductor ...
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... SP points at the next available location on the stack which is the address that is one less than the address where the CCR was saved. The PC value that is stacked is the address of the instruction in the main program that would have executed next if the interrupt had not occurred. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration NOTE ...
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... CONDITION CODE REGISTER ACCUMULATOR * INDEX REGISTER (LOW BYTE X) PROGRAM COUNTER HIGH PROGRAM COUNTER LOW TOWARD HIGHER ADDRESSES * High byte (H) of index register is not automatically stacked. Figure 5-1. Interrupt Stack Frame MC9S08AW60 Data Sheet, Rev 2 SP AFTER INTERRUPT STACKING SP BEFORE THE INTERRUPT Freescale Semiconductor ...
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... CCR the CPU will finish the current instruction, stack the PCL, PCH and CCR CPU registers, set the I bit, and then fetch the interrupt vector for the highest priority pending interrupt. Processing then continues in the interrupt service routine. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration NOTE ...
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... TPM1 channel 5 CH4IE TPM1 channel 4 CH3IE TPM1 channel 3 CH2IE TPM1 channel 2 CH1IE TPM1 channel 1 CH0IE TPM1 channel 0 LOLRE/LOCRE ICG LVDIE Low-voltage detect IRQIE IRQ pin — Software interrupt COPE Watchdog timer LVDRE Low-voltage detect — External pin — Illegal opcode Freescale Semiconductor ...
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... MCUs, the COP watchdog. To use an external clock source, it must be available and active. The RTICLKS bit in SRTISC is used to select the RTI clock source. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration level. Both the POR bit and the LVD bit in SRS are set ...
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... Refer to the direct-page register summary in address assignments for all registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. Some control bits in the SOPT and SPMSC2 registers are related to modes of operation. Although brief descriptions of these bits are provided here, the related functions are discussed in greater detail in Chapter 3, “ ...
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... The IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt request events. See Section 5.5.2.2, “Edge and Level 0 IRQ event on falling edges or rising edges only. 1 IRQ event on falling edges and low levels or on rising edges and high levels. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration ...
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... ENBDM = 0 in the BDCSC register. 0 Reset not caused by an illegal opcode. 1 Reset caused by an illegal opcode COP ILOP (1) (1) Figure 5-3. System Reset Status (SRS) Table 5-3. SRS Register Field Descriptions Description MC9S08AW60 Data Sheet, Rev ICG LVD ( Freescale Semiconductor ...
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... SOPT should be written during the user’s reset initialization program to set the desired controls even if the desired settings are the same as the reset settings. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration Description ...
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... MPE is set, the pin is driven low. See MCLK frequency = Bus Clock frequency ÷ MCSEL STOPE 0 1 Table 5-5. SOPT Register Field Descriptions Description 13 cycles of BUSCLK). 18 cycles of BUSCLK MPE 0 0 Description Equation 5-1. MC9S08AW60 Data Sheet, Rev MCSEL Freescale Semiconductor Eqn. 5-1 ...
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... Table 5-8. SDIDL Register Field Descriptions Field 7:0 Part Identification Number — Each derivative in the HCS08 family has a unique identification number. The ID[7:0] MC9S08AW60 Series is hard coded to the value $008. See also ID bits in Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration ID11 — ...
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... See Appendix A, “Electrical Characteristics and Timing RTI MC9S08AW60 Data Sheet, Rev RTIS2 RTIS1 Using External Clock Source Delay (Crystal Frequency) Disable periodic wakeup timer divide by 256 divide by 1024 divide by 2048 divide by 4096 divide by 8192 divide by 16384 divide by 32768 Freescale Semiconductor 0 RTIS0 0 ...
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... Bandgap Buffer Enable — The BGBE bit is used to enable an internal buffer for the bandgap voltage reference BGBE for use by the ADC module on one of its internal channels. 0 Bandgap buffer disabled. 1 Bandgap buffer enabled. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration ...
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... Stop2, partial power down, mode enabled PPDF LVDV LVWV transitions below the trip point or after reset and V Supply Description = V ). LVD LVDL = V ). LVD LVDH = V ). LVW LVWL = V ). LVW LVWH MC9S08AW60 Data Sheet, Rev PPDC PPDACK Unaffected by reset is already below V . Supply LVW ). LVD ). LVW Freescale Semiconductor ...
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... Features Parallel I/O and Pin Control features, depending on package choice, include: • A total of 54 general-purpose I/O pins in seven ports • Hysteresis input buffers • Software-controlled pullups on each input pin Freescale Semiconductor Table 6-1. KBI and Parallel I/O Interaction KBIPEn KBEDGn (KBI Pin Enable) ...
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... Control” for more information about pin control PTB6/ PTB5/ PTB4/ AD1P6 AD1P5 AD1P4 Figure 6-2. Port B Pin Names MC9S08AW60 Data Sheet, Rev 2 Connections,” for available Bit 0 PTA3 PTA2 PTA1 PTA0 Bit 0 PTB3/ PTB2/ PTB1/ PTB0/ AD1P3 AD1P2 AD1P1 AD1P0 Freescale Semiconductor ...
Page 83
... Port D pins are general-purpose I/O pins. Parallel I/O function is controlled by the port D data (PTDD) and data direction (PTDDD) registers which are located in page zero register space. The pin control registers, Freescale Semiconductor Control” for more information about Section 6.5, “Pin Control” ...
Page 84
... Control” for more information about pin control. (S08SCIV2)” (S08SPIV3)” for more information about using port E (S08TPMV2)” for more information about using port E pins as TPM MC9S08AW60 Data Sheet, Rev Bit 0 PTE3/ PTE2/ PTE1/ PTE0/ TPM1CH0 RxD1 TxD1 for more information about using Freescale Semiconductor ...
Page 85
... PTG5 and PTG6 function as oscillator pins. In this case the associated parallel I/O and pin control registers have no control of the pins. Refer to Chapter 8, “Internal Clock Generator as XTAL and EXTAL pins. Refer to Chapter 9, “Keyboard Interrupt keyboard inputs. Freescale Semiconductor PTF5/ PTF4/ PTF6 TPM2CH1 ...
Page 86
... This ensures that the pin will not be driven momentarily with an old data value that happened the port data register. 86 PTxDDn D Q PTxDn Figure 6-8. Parallel I/O Block Diagram MC9S08AW60 Data Sheet, Rev 2 Output Enable Output Data Input Data Synchronizer Freescale Semiconductor ...
Page 87
... DC behavior of I/O pins. However, the AC behavior is also affected. High drive allows a pin to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load. Because of this the EMC emissions may be affected by enabling pins as high drive. Freescale Semiconductor MC9S08AW60 Data Sheet, Rev 2 Chapter 6 Parallel Input/Output ...
Page 88
... Chapter 4, “Memory,” for the absolute address assignments for all parallel I/O and pin control registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file normally is used to translate these names into the appropriate absolute addresses. 6.7.1 Port A I/O Registers (PTAD and PTADD) Port A parallel I/O function is controlled by the registers listed below ...
Page 89
... PTA pin. For port A pins that are configured as outputs, these bits have no effect and the internal pullup devices are disabled. 0 Internal pullup device disabled for port A bit n. 1 Internal pullup device enabled for port A bit n. Freescale Semiconductor ...
Page 90
... PTA pin. 0 Low output drive enabled for port A bit n. 1 High output drive enabled for port A bit PTASE5 PTASE4 PTASE3 Description PTADS5 PTADS4 PTADS3 Description MC9S08AW60 Data Sheet, Rev PTASE2 PTASE1 PTASE0 PTADS2 PTADS1 PTADS0 Freescale Semiconductor ...
Page 91
... Data Direction for Port B Bits — These read/write bits control the direction of port B pins and what is read for PTBDD[7:0] PTBD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn. Freescale Semiconductor 5 4 PTBD5 PTBD4 ...
Page 92
... PTB pin. For port B pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port B bit n. 1 Output slew rate control enabled for port B bit PTBPE5 PTBPE4 PTBPE3 Description PTBSE5 PTBSE4 PTBSE3 Description MC9S08AW60 Data Sheet, Rev PTBPE2 PTBPE1 PTBPE0 PTBSE2 PTBSE1 PTBSE0 Freescale Semiconductor ...
Page 93
... Output Drive Strength Selection for Port B Bits — Each of these control bits selects between low and high PTBDS[7:0] output drive for the associated PTB pin. 0 Low output drive enabled for port B bit n. 1 High output drive enabled for port B bit n. Freescale Semiconductor PTBDS5 ...
Page 94
... Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn PTCD5 PTCD4 PTCD3 Figure 6-19. Port C Data Register (PTCD) Description PTCDD5 PTCDD4 PTCDD3 Description MC9S08AW60 Data Sheet, Rev PTCD2 PTCD1 PTCD0 PTCDD2 PTCDD1 PTCDD0 Freescale Semiconductor ...
Page 95
... PTCSE[6:0] rate control is enabled for the associated PTC pin. For port C pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port C bit n. 1 Output slew rate control enabled for port C bit n. Freescale Semiconductor PTCPE5 ...
Page 96
... Output Drive Strength Selection for Port C Bits — Each of these control bits selects between low and high PTCDS[6:0] output drive for the associated PTC pin. 0 Low output drive enabled for port C bit n. 1 High output drive enabled for port C bit PTCDS5 PTCDS4 PTCDS3 Description MC9S08AW60 Data Sheet, Rev PTCDS2 PTCDS1 PTCDS0 Freescale Semiconductor ...
Page 97
... Data Direction for Port D Bits — These read/write bits control the direction of port D pins and what is read for PTDDD[7:0] PTDD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn. Freescale Semiconductor PTDD5 ...
Page 98
... PTD pin. For port D pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port D bit n. 1 Output slew rate control enabled for port D bit PTDPE5 PTDPE4 PTDPE3 Description PTDSE5 PTDSE4 PTDSE3 Description MC9S08AW60 Data Sheet, Rev PTDPE2 PTDPE1 PTDPE0 PTDSE2 PTDSE1 PTDSE0 Freescale Semiconductor ...
Page 99
... Output Drive Strength Selection for Port D Bits — Each of these control bits selects between low and high PTDDS[7:0] output drive for the associated PTD pin. 0 Low output drive enabled for port D bit n. 1 High output drive enabled for port D bit n. Freescale Semiconductor PTDDS5 ...
Page 100
... Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port E bit n and PTED reads return the contents of PTEDn. 100 PTED5 PTED4 PTED3 Figure 6-29. Port E Data Register (PTED) Description PTEDD5 PTEDD4 PTEDD3 Description MC9S08AW60 Data Sheet, Rev PTED2 PTED1 PTED0 PTEDD2 PTEDD1 PTEDD0 Freescale Semiconductor ...
Page 101
... PTESE[7:0] rate control is enabled for the associated PTE pin. For port E pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port E bit n. 1 Output slew rate control enabled for port E bit n. Freescale Semiconductor PTEPE5 ...
Page 102
... Output Drive Strength Selection for Port E Bits — Each of these control bits selects between low and high PTEDS[7:0] output drive for the associated PTE pin. 0 Low output drive enabled for port E bit n. 1 High output drive enabled for port E bit n. 102 PTEDS5 PTEDS4 PTEDS3 Description MC9S08AW60 Data Sheet, Rev PTEDS2 PTEDS1 PTEDS0 Freescale Semiconductor ...
Page 103
... Data Direction for Port F Bits — These read/write bits control the direction of port F pins and what is read for PTFDD[7:0] PTFD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port F bit n and PTFD reads return the contents of PTFDn. Freescale Semiconductor PTFD5 ...
Page 104
... PTF pin. For port F pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port F bit n. 1 Output slew rate control enabled for port F bit n. 104 PTFPE5 PTFPE4 PTFPE3 Description PTFSE5 PTFSE4 PTFSE3 Description MC9S08AW60 Data Sheet, Rev PTFPE2 PTFPE1 PTFPE0 PTFSE2 PTFSE1 PTFSE0 Freescale Semiconductor ...
Page 105
... Output Drive Strength Selection for Port F Bits — Each of these control bits selects between low and high PTFDS[7:0] output drive for the associated PTF pin. 0 Low output drive enabled for port F bit n. 1 High output drive enabled for port F bit n. Freescale Semiconductor PTFDS5 ...
Page 106
... Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn. 106 PTGD5 PTGD4 PTGD3 Figure 6-39. Port G Data Register (PTGD) Description PTGDD5 PTGDD4 PTGDD3 Description MC9S08AW60 Data Sheet, Rev PTGD2 PTGD1 PTGD0 PTGDD2 PTGDD1 PTGDD0 Freescale Semiconductor ...
Page 107
... PTGSE[6:0] rate control is enabled for the associated PTG pin. For port G pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port G bit n. 1 Output slew rate control enabled for port G bit n. Freescale Semiconductor PTGPE5 ...
Page 108
... Output Drive Strength Selection for Port G Bits — Each of these control bits selects between low and high PTGDS[6:0] output drive for the associated PTG pin. 0 Low output drive enabled for port G bit n. 1 High output drive enabled for port G bit n. 108 PTGDS5 PTGDS4 PTGDS3 Description MC9S08AW60 Data Sheet, Rev PTGDS2 PTGDS1 PTGDS0 Freescale Semiconductor ...
Page 109
... This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several instructions and enhanced addressing modes were added to improve C compiler effi ...
Page 110
... For compatibility with the earlier M68HC05 family forced to 0x00 during reset. Reset has no effect on the contents of X. 110 7 0 ACCUMULATOR A 16-BIT INDEX REGISTER H:X INDEX REGISTER (LOW STACK POINTER PROGRAM COUNTER CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-1. CPU Registers MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor ...
Page 111
... Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code bits in general terms. For a more detailed explanation of how each instruction sets the CCR bits, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMv1. ...
Page 112
... No carry out of bit 7 1 Carry out of bit 7 112 CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-2. Condition Code Register Table 7-1. CCR Register Field Descriptions Description MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor ...
Page 113
... This is faster and more memory efficient than specifying a complete 16-bit address for the operand. Freescale Semiconductor Chapter 7 Central Processor Unit (S08CPUV2) MC9S08AW60 Data Sheet, Rev 2 ...
Page 114
... SP-Relative, 8-Bit Offset (SP1) This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. 114 MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor ...
Page 115
... After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts while in the interrupt service routine. Although it is possible to clear the I bit with an instruction in the Freescale Semiconductor Chapter 7 Central Processor Unit (S08CPUV2) Resets, Interrupts, and System Configuration ...
Page 116
... MCU even stop mode. Recovery from stop mode depends on the particular HCS08 and whether the oscillator was stopped in stop mode. Refer to the Modes of Operation 116 chapter for more details. MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor ...
Page 117
... Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the BGND opcode. When the program reaches this breakpoint address, the CPU is forced to active background mode rather than continuing the user program. Freescale Semiconductor Chapter 7 Central Processor Unit (S08CPUV2) MC9S08AW60 Data Sheet, Rev 2 ...
Page 118
... Condition code register (CCR) bits V = Two’s complement overflow indicator, bit Half carry, bit Interrupt mask, bit Negative indicator, bit Zero indicator, bit Carry/borrow, bit 0 (carry out of bit 7) CCR activity notation – = Bit not affected 118 MC9S08AW60 Data Sheet, Rev 2 Table 7-2. Freescale Semiconductor ...
Page 119
... Address modes INH = Inherent (no operands) IMM = 8-bit or 16-bit immediate DIR = 8-bit direct EXT = 16-bit extended Freescale Semiconductor Chapter 7 Central Processor Unit (S08CPUV2) MC9S08AW60 Data Sheet, Rev 2 119 ...
Page 120
... IMM AB ii DIR BB dd EXT IX2 IX1 SP2 9EDB ee ff SP1 9EEB IMM A4 ii DIR B4 dd EXT IX2 IX1 SP2 9ED4 ee ff SP1 9EE4 ff DIR 38 dd INH 48 INH 58 IX1 SP1 9E68 ff DIR 37 dd INH 47 INH 57 IX1 SP1 9E67 Freescale Semiconductor ...
Page 121
... BMS rel Set BNE rel Branch if Not Equal BPL rel Branch if Plus BRA rel Branch Always Freescale Semiconductor Chapter 7 Central Processor Unit (S08CPUV2) Description ← 0 – – – – – – – – – – – – Branch if ( – – – – – – ...
Page 122
... INH 4F INH 5F INH 8C IX1 SP1 9E6F ff IMM A1 ii DIR B1 dd EXT IX2 ↕ ↕ ↕ IX1 SP2 9ED1 ee ff SP1 9EE1 ff DIR 33 dd INH 43 INH 53 ↕ ↕ 1 IX1 SP1 9E63 ff EXT IMM ↕ ↕ ↕ DIR 75 dd SP1 9EF3 ff Freescale Semiconductor ...
Page 123
... LDA ,X LDA oprx16,SP LDA oprx8,SP LDHX #opr16i LDHX opr8a LDHX opr16a Load Index Register (H:X) LDHX ,X from Memory LDHX oprx16,X LDHX oprx8,X LDHX oprx8,SP Freescale Semiconductor Description (X) – (M) ↕ – – (CCR Updated But Operands Not Changed) U – – (A) 10 Decrement Branch if (result) ≠ ...
Page 124
... IX1 SP1 9E60 ff INH 9D INH 62 IMM AA ii DIR BA dd EXT IX2 ↕ ↕ – IX1 SP2 9EDA ee ff SP1 9EEA ff INH 87 INH 8B INH 89 INH 86 INH 8A INH 88 DIR 39 dd INH 49 INH 59 ↕ ↕ ↕ IX1 SP1 9E69 ff Freescale Semiconductor ...
Page 125
... SUB #opr8i SUB opr8a SUB opr16a SUB oprx16,X Subtract SUB oprx8,X SUB ,X SUB oprx16,SP SUB oprx8,SP SWI Software Interrupt Freescale Semiconductor Chapter 7 Central Processor Unit (S08CPUV2) Description ↕ C – – ← 0xFF – – – – – – (High Byte Not Affected) SP ← ...
Page 126
... SP ← (H:X) – 0x0001 – – – – – – I bit ← 0; Halt CPU – – 0 – – – MC9S08AW60 Data Sheet, Rev 2 Effect on CCR 84 INH 97 INH 85 DIR 3D dd INH 4D INH 5D ↕ ↕ – IX1 SP1 9E6D ff INH 95 INH 9F INH 94 INH 8F Freescale Semiconductor ...
Page 127
... IMM Immediate IX Indexed, No Offset DIR Direct IX1 Indexed, 8-Bit Offset EXT Extended IX2 Indexed, 16-Bit Offset DD DIR to DIR IMD IMM to DIR IX+D IX+ to DIR DIX+ DIR to IX+ Freescale Semiconductor Table 7-3. Opcode Map (Sheet Read-Modify-Write Control NEGX NEG NEG RTI 1 INH ...
Page 128
... IX 4 IX2 3 IX1 4 SP2 3 9EDF 5 9EEF STX 4 SP2 3 Prebyte (9E) and Opcode in 9E60 6 HCS08 Cycles Hexadecimal NEG Instruction Mnemonic Addressing Mode Number of Bytes 3 SP1 Freescale Semiconductor 4 SUB SP1 4 CMP SP1 4 SBC SP1 4 9EF3 6 CPX CPHX SP1 3 SP1 4 AND SP1 4 BIT SP1 4 LDA ...
Page 129
... CPU * ICGLCLK is the alternate BDC clock source for the MC9S08AW60 Series. Figure 8-1. System Clock Distribution Diagram Freescale Semiconductor recommends that FLASH location $FFBE be reserved to store a nonvolatile version of ICGTRM. This will allow debugger and programmer vendors to perform a manual trim operation and store the resultant ICGTRM value for users to access at a later time ...
Page 130
... PTB0/AD1P0 PTC6 PTC5/RxD2 PTC4 PTC3/TxD2 PTC2/MCLK PTC1/SDA1 PTC0/SCL1 8 PTD7/AD1P15/KBI1P7 PTD6/AD1P14/TPM1CLK PTD5/AD1P13 PTD4/AD1P12/TPM2CLK PTD3/AD1P11/KBI1P6 PTD2/AD1P10/KBI1P5 PTD1/AD1P9 PTD0/AD1P8 PTE7/SPSCK1 PTE6/MOSI1 PTE5/MISO1 PTE4/SS1 PTE3/TPM1CH1 PTE2/TPM1CH0 6 PTE1/RxD1 PTE0/TxD1 PTF7 PTF6 PTF5/TPM2CH1 PTF4/TPM2CH0 2 PTF3/TPM1CH5 3 PTF2/TPM1CH4 PTF1/TPM1CH3 PTF0/TPM1CH2 5 PTG6/EXTAL PTG5/XTAL PTG4/KBI1P4 PTG3/KBI1P3 PTG2/KBI1P2 PTG1/KBI1P1 . DD PTG0/KBI1P0 Freescale Semiconductor ...
Page 131
... Frequency-locked loop (FLL) generates 8 MHz to 40 MHz (for bus rates MHz) — Uses external or internal clock as reference frequency • Automatic lockout of non-running clock sources • Reset or interrupt on loss of clock or loss of FLL lock Freescale Semiconductor Chapter 8 Internal Clock Generator (S08ICGV4) Section 8.5, “Initialization/Application MC9S08AW60 Data Sheet, Rev 2 Figure 8-3, the ICG consists ...
Page 132
... The FLL DCO frequency is off target and the FLL is adjusting the DCO to match the target frequency. — FLL engaged external locked is a state which occurs when the FLL detects that the DCO is locked to a multiple of the internal reference. 132 MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor ...
Page 133
... XTAL — Oscillator Output If upon the first write to ICGC1, either the FEE mode or FBE mode is selected, this pin functions as the output of the oscillator circuit. If upon the first write to ICGC1, either the FEI mode or SCM mode is Freescale Semiconductor ICG SELECT ICGERCLK ...
Page 134
... Recommended component values are listed in the Figure 8-5. External Frequency Reference Connection 134 ICG EXTAL V SS CLOCK INPUT Figure 8-4. External Clock Connections ICG EXTAL CRYSTAL OR RESONATOR MC9S08AW60 Data Sheet, Rev 2 Figure 8-4. XTAL NOT CONNECTED Electrical Characteristics chapter. XTAL R S Freescale Semiconductor ...
Page 135
... Register Definition Refer to the direct-page register summary in the assignments for all ICG registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 8.3.1 ICG Control Register 1 (ICGC1) ...
Page 136
... Oscillator disabled when ICG is in off mode unless ENABLE is high, CLKS = 10, and REFST = 1. 1 Oscillator enabled when ICG is in off mode, CLKS = 1X and REFST = 1. 1 Loss of Clock Disable LOCD 0 Loss of clock detection enabled. 1 Loss of clock detection disabled. 136 Description MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor ...
Page 137
... Writes to the RFD bits will not take effect if a previous write is not complete. 000 Division factor = 1 001 Division factor = 2 010 Division factor = 4 011 Division factor = 8 100 Division factor = 16 101 Division factor = 32 110 Division factor = 64 111 Division factor = 128 Freescale Semiconductor MFD LOCRE Figure 8-7 ...
Page 138
... Writing a logic 0 to ICGIF has no effect ICG interrupt request is pending ICG interrupt request is pending. 138 REFST LOLS LOCK Figure 8-8. ICG Status Register 1 (ICGS1) Description MC9S08AW60 Data Sheet, Rev LOCS ERCS ICGIF Freescale Semiconductor ...
Page 139
... FLT read only except when the CLKS bits are programmed to self-clocked mode (CLKS = 00). In self-clocked mode, any write to ICGFLTU updates the current 12-bit filter value. Writes to the ICGFLTU register will not affect FLT if a previous latch sequence is not complete. Freescale Semiconductor ...
Page 140
... When using the FLL, configure the ICG so that the frequency of ICGDCLK does not exceed its maximum value to ensure proper MCU operation. 140 FLT Description TRIM Figure 8-12. ICG Trim Register (ICGTRM) Description MC9S08AW60 Data Sheet, Rev Freescale Semiconductor ...
Page 141
... FLL engaged external (either by programming CLKS or due to a loss of external reference clock), f will maintain the previous frequency, but ICGOUT will double if the FLL was unlocked. ICGDCLK If this mode is entered from off mode, f Freescale Semiconductor Chapter 8 Internal Clock Generator (S08ICGV4) will default to f ICGDCLK Self_reset will maintain the previous frequency ...
Page 142
... DIGITAL DIGITALLY CONTROLLED LOOP OSCILLATOR FILTER FLL ANALOG CLKST PULSE COUNTER RESET AND INTERRUPT CONTROL LOCS ERCS LOCD ICGIF LOLRE MC9S08AW60 Data Sheet, Rev 2 RFD REDUCED ICGOUT FREQUENCY DIVIDER (R) ICGDCLK 1x 2x FREQUENCY- LOCKED LOOP (FLL) ICG2DCLK IRQ RESET LOCRE Freescale Semiconductor ...
Page 143
... MHz in FEE mode to prevent over-clocking the DCO. The minimum multiplier for the FLL, from operational limit of the DCO, the reference clock cannot be any faster than 10 MHz. Freescale Semiconductor or less than the minimum n unlock (max) and greater than n ...
Page 144
... If Δn goes outside this range unexpectedly, unlock MC9S08AW60 Data Sheet, Rev 2 or less than lock / (2×R) This ICGDCLK (max) and greater lock /R. In FLL engaged external ICGDCLK (max). After the FLL has locked, Δn must Freescale Semiconductor ...
Page 145
... If ENABLE is high (waiting for external crystal start-up after exiting stop). 2 DCO clock will not be monitored until DCOS = 1 upon entering SCM from off or FLL bypassed external mode. Freescale Semiconductor and f , respectively, the LOCS status bit will be set to indicate the error. LOD ...
Page 146
... SCM ICGDCLK/R — ICGDCLK/R — DCOS = 0 or ICGDCLK/R — ICGDCLK/R DCOS = 1 ICGDCLK/R — ERCS = 1 — ERCS = 1 and 3 DCOS = 1 ERCS = 1 and (2) DCOS = 1 Freescale Semiconductor Reason CLKS1 ≠ CLKST — ERCS = 0 — DCOS = 0 ERCS = 0 ERCS = 0 — ERCS = 0 — LOCS = 1 & ERCS = 1 — — ...
Page 147
... For other applications, lowest power consumption may be the chief clock consideration. Still others may have lowest cost as the primary goal. The ICG allows great flexibility in choosing which is best for any application. Freescale Semiconductor Chapter 8 Internal Clock Generator (S08ICGV4) Table Table 8-12) ...
Page 148
... MC9S08AW60 Data Sheet, Rev 2 Clock Reference Source = External < 20 MHz Bus range ≤ 8 MHz when crystal or resonator is P Note NA Typical f ICGOUT immediately after reset NA 64 Typical f = 243 kHz IRG . Division Factor (R) ÷1 ÷2 ÷4 ÷8 ÷16 Freescale Semiconductor = 8 MHz ...
Page 149
... This is read only; should read DCOS = 1 before performing any time critical tasks ICGFLTLU/L = $xx Only needed in self-clocked mode; FLT will be adjusted by loop to give 8.38 MHz DCO clock Bits 15:12 unused 0000 Freescale Semiconductor Table 8-12. MFD and RFD Decode Table 101 110 111 = ...
Page 150
... CHECK NO FLL LOCK STATUS. LOCK = 1? YES CONTINUE NOTE: THIS WILL REQUIRE THE OSCILLATOR TO START AND STABILIZE. ACTUAL TIME IS DEPENDENT ON CRYSTAL /RESONATOR AND EXTERNAL CIRCUITRY. MC9S08AW60 Data Sheet, Rev 2 RECOVERY FROM STOP OSCSTEN = 0 CHECK NO FLL LOCK STATUS. LOCK = 1? YES CONTINUE Freescale Semiconductor ...
Page 151
... This is read only except for clearing interrupt flag ICGS2 = $xx This is read only. Should read DCOS before performing any time critical tasks ICGFLTLU/L = $xx Not used in this example ICGTRM Not used in this example Freescale Semiconductor = 4.00 MHz ext ext Configures oscillator for low power Configures oscillator for high-frequency range ...
Page 152
... FLL LOCK STATUS Figure 8-15. ICG Initialization and Stop Recovery for Example #2 152 RECOVERY RESET FROM STOP INITIALIZE ICG SERVICE INTERRUPT ICGC1 = $7A ICGC2 = $30 SOURCE (f CHECK NO LOCK = 1? FLL LOCK STATUS LOCK = 1? YES CONTINUE CONTINUE MC9S08AW60 Data Sheet, Rev MHz) Bus CHECK NO YES Freescale Semiconductor ...
Page 153
... This is read only except for clearing interrupt flag ICGS2 = $xx This is read only; good idea to read this before performing time critical operations ICGFLTLU/L = $xx Not used in this example Freescale Semiconductor / 64, f IRG IRG Configures oscillator for low power Configures oscillator for low-frequency range; FLL prescale factor is 64 Oscillator using crystal or resonator requested (bit is really a don’ ...
Page 154
... Only need to write when trimming internal oscillator; done in separate operation (see example #4) NO YES NOTE: THIS WILL REQUIRE THE INTERAL REFERENCE CLOCK TO START AND STABILIZE. MC9S08AW60 Data Sheet, Rev 2 RECOVERY FROM STOP CHECK NO FLL LOCK STATUS. LOCK = 1? YES CONTINUE Freescale Semiconductor ...
Page 155
... If the intended bus frequency is near the maximum allowed for the device recommended to trim using a reduction divisor (R) twice the final value. After the trim procedure is complete, the reduction divisor can be restored. This will prevent accidental overshoot of the maximum clock frequency. Freescale Semiconductor START TRIM PROCEDURE ICGTRM = $80 ...
Page 156
... Chapter 8 Internal Clock Generator (S08ICGV4) 156 MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor ...
Page 157
... PTxPEn PTxDDn (Pull Enable) (Data Direction Don’t care Freescale Semiconductor Connections,” for more information about the logic and Table 9-1. KBI and Parallel I/O Interaction KBIPEn KBEDGn (KBI Pin Enable) (KBI Edge Select ...
Page 158
... Four falling edge/low level sensitive • Four falling edge/low level or rising edge/high level sensitive • Choice of edge-only or edge-and-level sensitivity • Common interrupt flag and interrupt enable control • Capable of waking up the MCU from stop3 or wait mode 158 MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor ...
Page 159
... Pin contains integrated pullup device. 5. Pins PTD7, PTD3, PTD2, and PTG4 contain both pullup and pulldown devices. Pulldown enabled when KBI is enabled (KBIPEn = 1) and rising edge is selected (KBEDGn = 1). Figure 9-1. Block Diagram Highlighting KBI Module Freescale Semiconductor DEBUG MODULE (DBG) RxD2 SERIAL COMMUNICATIONS ...
Page 160
... Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all KBI registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. ...
Page 161
... KBI port bits 3 through 0 can detect falling edges-only or falling edges and low levels. KBI port bits 7 through 4 can be configured to detect either: • Rising edges-only or rising edges and high levels (KBEDGn = 1) • Falling edges-only or falling edges and low levels (KBEDGn = 0) 0 Edge-only detection 1 Edge-and-level detection Freescale Semiconductor KBF KBEDG5 ...
Page 162
... When the MCU enters stop3 mode, the synchronous edge-detection logic is bypassed (because clocks are stopped). In stop3 mode, KBI inputs act as asynchronous level-sensitive inputs so they can wake the MCU from stop3 mode. 162 KBIPE5 KBIPE4 KBIPE3 Description MC9S08AW60 Data Sheet, Rev KBIPE2 KBIPE1 KBIPE0 Freescale Semiconductor ...
Page 163
... When KBIMOD = 0 (selecting edge-only operation), KBF is always cleared by writing 1 to KBACK. When KBIMOD = 1 (selecting edge-and-level operation), KBF cannot be cleared as long as any keyboard input is at its asserted level. Freescale Semiconductor MC9S08AW60 Data Sheet, Rev 2 Chapter 9 Keyboard Interrupt (S08KBIV1) 163 ...
Page 164
... Chapter 9 Keyboard Interrupt (S08KBIV1) 164 MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor ...
Page 165
... Timer system enable • One interrupt per channel plus a terminal count interrupt for each TPM module Freescale Semiconductor MC9S08AW60 Data Sheet, Rev 2 Section 8.4.11, “Fixed 165 ...
Page 166
... PTB0/AD1P0 PTC6 PTC5/RxD2 PTC4 PTC3/TxD2 PTC2/MCLK PTC1/SDA1 PTC0/SCL1 8 PTD7/AD1P15/KBI1P7 PTD6/AD1P14/TPM1CLK PTD5/AD1P13 PTD4/AD1P12/TPM2CLK PTD3/AD1P11/KBI1P6 PTD2/AD1P10/KBI1P5 PTD1/AD1P9 PTD0/AD1P8 PTE7/SPSCK1 PTE6/MOSI1 PTE5/MISO1 PTE4/SS1 PTE3/TPM1CH1 PTE2/TPM1CH0 6 PTE1/RxD1 PTE0/TxD1 PTF7 PTF6 PTF5/TPM2CH1 PTF4/TPM2CH0 2 PTF3/TPM1CH5 3 PTF2/TPM1CH4 PTF1/TPM1CH3 PTF0/TPM1CH2 5 PTG6/EXTAL PTG5/XTAL PTG4/KBI1P4 PTG3/KBI1P3 PTG2/KBI1P2 PTG1/KBI1P1 . DD PTG0/KBI1P0 Freescale Semiconductor ...
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... Set, clear, or toggle output compare action — Selectable polarity on PWM outputs 10.2.2 Block Diagram Figure 10-2 shows the structure of a TPM. Some MCUs include more than one TPM, with various numbers of channels. Freescale Semiconductor Chapter 10 Timer/Pulse-Width Modulator (S08TPMV2) MC9S08AW60 Data Sheet, Rev 2 167 ...
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... MS1B MS1A ELSnB ELSnA CHnF CHnIE MSnA MSnB Figure 10-2. TPM Block Diagram MC9S08AW60 Data Sheet, Rev 2 DIVIDE BY PS1 PS0 TOF INTERRUPT LOGIC TOIE PORT TPMxCH0 LOGIC INTERRUPT LOGIC TPMxCH1 PORT LOGIC INTERRUPT LOGIC TPMxCHn PORT LOGIC INTERRUPT LOGIC Freescale Semiconductor ...
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... A 16-bit channel value register (TPMxCnVH:TPMxCnVL) Refer to the direct-page register summary in the assignments for all TPM registers. This section refers to registers and control bits only by their names. A Freescale Semiconductor Chapter 10 Timer/Pulse-Width Modulator (S08TPMV2) Pins and Connections Memory chapter of this data sheet for the absolute address ...
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... Chapter 10 Timer/Pulse-Width Modulator (S08TPMV2) Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. Some MCU systems have more than one TPM, so register names include placeholder characters to identify which TPM and which channel is being referenced. For example, TPMxCnSC refers to timer (TPM) x, channel n and TPM1C2SC is the status and control register for timer 1, channel 2 ...
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... Bit Reset 0 0 Figure 10-4. Timer x Counter Register High (TPMxCNTH) Freescale Semiconductor Chapter 10 Timer/Pulse-Width Modulator (S08TPMV2) Table 10-2. TPM Clock Source Selection TPM Clock Source to Prescaler Input No clock selected (TPMx disabled) Bus rate clock (BUSCLK) Fixed system clock (XCLK) External source (TPMxCLK) Table 10-3 ...
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... An alternative approach is to reset the TPM counter before writing to the TPM modulo registers to avoid confusion about when the first counter overflow will occur. 172 Any write to TPMxCNTL clears the 16-bit counter MC9S08AW60 Data Sheet, Rev Bit Bit Bit Freescale Semiconductor ...
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... This function is typically used to temporarily disable an input capture channel or to make the timer pin available as a general-purpose I/O pin when the associated timer channel is set software timer that does not require the use of a pin. Freescale Semiconductor Chapter 10 Timer/Pulse-Width Modulator (S08TPMV2) 5 ...
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... Toggle output on compare 10 Clear output on compare 11 Set output on compare 10 Edge-aligned High-true pulses (clear output on compare) PWM X1 Low-true pulses (set output on compare) 10 Center-aligned High-true pulses (clear output on compare-up) PWM X1 Low-true pulses (set output on compare-up MC9S08AW60 Data Sheet, Rev 2 Configuration Bit Bit Freescale Semiconductor ...
Page 175
... Otherwise, the counter operates as a simple up-counter up-counter, the main 16-bit counter counts from 0x0000 through its terminal count and then continues with 0x0000. The terminal count is 0xFFFF or a modulus value in TPMxMODH:TPMxMODL. Freescale Semiconductor Chapter 10 Timer/Pulse-Width Modulator (S08TPMV2) Section 10.4.1, “Timer x Status and Control Register MC9S08AW60 Data Sheet, Rev 2 (TPMxSC)” ...
Page 176
... When either byte of the 16-bit capture register is read, both bytes are latched into a buffer to support coherent 16-bit accesses regardless of order. The coherency sequence can be manually reset by writing to the channel status/control register (TPMxCnSC). An input capture event sets a flag bit (CHnF) that can optionally generate a CPU interrupt request. 176 MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor ...
Page 177
... TPMxCnVH or TPMxCnVL, write to buffer registers. In edge-PWM mode, values are transferred to the corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have been written and the value in the TPMxCNTH:TPMxCNTL counter is 0x0000. (The new duty cycle does not take effect until the next full period.) Freescale Semiconductor OVERFLOW PERIOD PULSE ...
Page 178
... TPMxMODH, TPMxMODL, TPMxCnVH, and TPMxCnVL, actually write to buffer registers. Values are 178 period = 2 x (TPMxMODH:TPMxMODL); for TPMxMODH:TPMxMODL = 0x0001–0x7FFF COUNT = 0 OUTPUT OUTPUT COMPARE COMPARE (COUNT UP) (COUNT DOWN) PULSE WIDTH 2 x PERIOD 2 x MC9S08AW60 Data Sheet, Rev 2 Eqn. 10-1 Eqn. 10-2 COUNT = TPMxMODH:TPMx Freescale Semiconductor ...
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... This corresponds to the end of a PWM period. (The 0x0000 count value corresponds to the center of a period.) Freescale Semiconductor Chapter 10 Timer/Pulse-Width Modulator (S08TPMV2) chapter for absolute interrupt vector addresses, priority, and local ...
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... The flag is cleared by the 2-step sequence described in 180 Flags.” Flags.” Section 10.6.1, “Clearing Timer Interrupt MC9S08AW60 Data Sheet, Rev 2 Flags.” Freescale Semiconductor ...
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... This SCI system offers many advanced features not commonly found on other asynchronous serial I/O peripherals on other embedded controllers. The receiver employs an advanced data sampling technique that ensures reliable communication and noise detection. Hardware parity, receiver wakeup, and double buffering on transmit and receive are also included. Freescale Semiconductor MC9S08AW60 Data Sheet, Rev 2 181 ...
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... PTB0/AD1P0 PTC6 PTC5/RxD2 PTC4 PTC3/TxD2 PTC2/MCLK PTC1/SDA1 PTC0/SCL1 8 PTD7/AD1P15/KBI1P7 PTD6/AD1P14/TPM1CLK PTD5/AD1P13 PTD4/AD1P12/TPM2CLK PTD3/AD1P11/KBI1P6 PTD2/AD1P10/KBI1P5 PTD1/AD1P9 PTD0/AD1P8 PTE7/SPSCK1 PTE6/MOSI1 PTE5/MISO1 PTE4/SS1 PTE3/TPM1CH1 PTE2/TPM1CH0 6 PTE1/RxD1 PTE0/TxD1 PTF7 PTF6 PTF5/TPM2CH1 PTF4/TPM2CH0 2 PTF3/TPM1CH5 3 PTF2/TPM1CH4 PTF1/TPM1CH3 PTF0/TPM1CH2 5 PTG6/EXTAL PTG5/XTAL PTG4/KBI1P4 PTG3/KBI1P3 PTG2/KBI1P2 PTG1/KBI1P1 . DD PTG0/KBI1P0 Freescale Semiconductor ...
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... Stop modes — SCI is halted during all stop modes • Loop mode • Single-wire mode 11.1.3 Block Diagram Figure 11-2 shows the transmitter portion of the SCI. Freescale Semiconductor Chapter 11 Serial Communications Interface (S08SCIV2) MC9S08AW60 Data Sheet, Rev 2 183 ...
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... SHIFT DIRECTION T8 PARITY GENERATION TRANSMIT CONTROL TDRE TIE TC TCIE Figure 11-2. SCI Transmitter Block Diagram MC9S08AW60 Data Sheet, Rev 2 LOOPS RSRC LOOP TO RECEIVE CONTROL DATA TxD PIN TXINV SCI CONTROLS TxD TO TxD PIN LOGIC TxD DIRECTION Tx INTERRUPT REQUEST Freescale Semiconductor ...
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... FROM TRANSMITTER PE PT 11.2 Register Definition The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for transmit/receive data. Freescale Semiconductor Chapter 11 Serial Communications Interface (S08SCIV2) (READ-ONLY) SCID – Rx BUFFER DIVIDE 11-BIT RECEIVE SHIFT REGISTER ...
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... Chapter 11 Serial Communications Interface (S08SCIV2) Refer to the direct-page register summary in the assignments for all SCI registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 11.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBHL) This pair of registers controls the prescale divisor for SCI baud rate generation. To update the 13-bit baud rate setting [SBR12:SBR0], fi ...
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... Parity Type — Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total PT number the data character, including the parity bit, is odd. Even parity means the total number the data character, including the parity bit, is even. 0 Even parity. 1 Odd parity. Freescale Semiconductor Chapter 11 Serial Communications Interface (S08SCIV2 RSRC ...
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... I/O pin. 2 Receiver Enable — When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin Receiver off. 1 Receiver on. 188 RIE ILIE Description Idle” for more details. MC9S08AW60 Data Sheet, Rev RWU SBK Freescale Semiconductor ...
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... TC is cleared automatically by reading SCIxS1 with and then doing one of the following three things: • Write to the SCI data register (SCIxD) to transmit new data • Queue a preamble by changing TE from • Queue a break character by writing 1 to SBK in SCIxC2 Freescale Semiconductor Chapter 11 Serial Communications Interface (S08SCIV2) Description Section 11.3.3.2, “Receiver Wakeup Section 11.3.2.1, “ ...
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... Parity Error Flag — set at the same time as RDRF when parity is enabled ( and the parity bit in PF the received character does not agree with the expected parity value. To clear PF, read SCIxS1 and then read the SCI data register (SCIxD parity error. 1 Parity error. 190 Description MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor ...
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... SCI shift register after SCIxD is written so T8 should be written (if it needs to change from its previous value) before SCIxD is written does not need to change in the new value (such as when it is used to generate mark or space parity), it need not be written each time SCIxD is written. Freescale Semiconductor Chapter 11 Serial Communications Interface (S08SCIV2) 5 ...
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... The transmitter and receiver operate independently, although they use the same baud rate generator. During normal operation, the MCU monitors the status of the SCI, writes the data to be transmitted, and processes received data. The following describes each of the blocks of the SCI. 192 Description Figure 11-11. SCI Data Register (SCIxD) MC9S08AW60 Data Sheet, Rev Freescale Semiconductor ...
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... For a Freescale Semiconductor SCI system whose bus frequency is driven by a crystal, the allowed baud rate mismatch is about ±4.5 percent for 8-bit data format and about ± ...
Page 194
... If SBK is still 1 when the queued break moves into the shifter (synchronized to the baud rate clock), an additional break character is queued. If the receiving device is another Freescale Semiconductor SCI, the break characters will be received all eight data bits and a framing error ( occurs. ...
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... Receiver wakeup is a hardware mechanism that allows an SCI receiver to ignore the characters in a message that is intended for a different SCI receiver. In such a system, all receivers evaluate the first Freescale Semiconductor Chapter 11 Serial Communications Interface (S08SCIV2) Modes.” For the remainder of this discussion, we assume the SCI MC9S08AW60 Data Sheet, Rev 2 Section 11 ...
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... SCIxD. If the transmit interrupt enable (TIE) bit is set, a hardware interrupt will be requested whenever TDRE = 1. Transmit complete (TC) indicates that the transmitter is finished transmitting all data, preamble, and break characters and is idle with TxD high. This flag is often used in 196 MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor ...
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... T8 is copied at the same time data is transferred from SCIxD to the shifter. When receiving 9-bit data, clear the RDRF bit by reading both R8 and SCIxD. R8 and SCIxD can be read in either order. Freescale Semiconductor Chapter 11 Serial Communications Interface (S08SCIV2) MC9S08AW60 Data Sheet, Rev 2 197 ...
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... TXDIR = 0, the TxD pin is an input to the SCI receiver and the transmitter is temporarily disconnected from the TxD pin so an external device can send serial data to the receiver. When TXDIR = 1, the TxD pin is an output driven by the transmitter. 198 MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor ...
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... The MC9S08AW60 Series has one serial peripheral interface (SPI) module. The four pins associated with SPI functionality are shared with port E pins 4–7. See Specifications,” for SPI electrical parametric information. Freescale Semiconductor Appendix A, “Electrical Characteristics and Timing MC9S08AW60 Data Sheet, Rev 2 ...
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... PTB0/AD1P0 PTC6 PTC5/RxD2 PTC4 PTC3/TxD2 PTC2/MCLK PTC1/SDA1 PTC0/SCL1 8 PTD7/AD1P15/KBI1P7 PTD6/AD1P14/TPM1CLK PTD5/AD1P13 PTD4/AD1P12/TPM2CLK PTD3/AD1P11/KBI1P6 PTD2/AD1P10/KBI1P5 PTD1/AD1P9 PTD0/AD1P8 PTE7/SPSCK1 PTE6/MOSI1 PTE5/MISO1 PTE4/SS1 PTE3/TPM1CH1 PTE2/TPM1CH0 6 PTE1/RxD1 PTE0/TxD1 PTF7 PTF6 PTF5/TPM2CH1 PTF4/TPM2CH0 2 PTF3/TPM1CH5 3 PTF2/TPM1CH4 PTF1/TPM1CH3 PTF0/TPM1CH2 5 PTG6/EXTAL PTG5/XTAL PTG4/KBI1P4 PTG3/KBI1P3 PTG2/KBI1P2 PTG1/KBI1P1 . DD PTG0/KBI1P0 Freescale Semiconductor ...