MC9S08AW32CFGE Freescale, MC9S08AW32CFGE Datasheet - Page 89
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MC9S08AW32CFGE
Manufacturer Part Number
MC9S08AW32CFGE
Description
Manufacturer
Freescale
Datasheet
1.MC9S08AW32CFGE.pdf
(324 pages)
Specifications of MC9S08AW32CFGE
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
40MHz
Interface Type
I2C/SCI/SPI
Total Internal Ram Size
2KB
# I/os (max)
34
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
LQFP
Program Memory Type
Flash
Program Memory Size
32KB
Lead Free Status / RoHS Status
Compliant
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6.7.2
In addition to the I/O control, port A pins are controlled by the registers listed below.
Freescale Semiconductor
PTADD[7:0]
PTAPE[7:0]
Reset
Reset
Field
Field
[7:0]
7:0
W
W
R
R
PTADD7
PTAPE7
Port A Pin Control Registers (PTAPE, PTASE, PTADS)
Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for
PTAD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
Internal Pullup Enable for Port A Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTA pin. For port A pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port A bit n.
1 Internal pullup device enabled for port A bit n.
0
0
7
7
PTADD6
PTAPE6
Figure 6-10. Data Direction for Port A Register (PTADD)
0
0
Figure 6-11. Internal Pullup Enable for Port A (PTAPE)
6
6
Table 6-3. PTADD Register Field Descriptions
Table 6-4. PTADD Register Field Descriptions
PTADD5
PTAPE5
0
0
5
5
MC9S08AW60 Data Sheet, Rev 2
PTADD4
PTAPE4
0
0
4
4
Description
Description
PTADD3
PTAPE3
3
0
3
0
PTADD2
PTAPE2
0
0
2
2
Chapter 6 Parallel Input/Output
PTADD1
PTAPE1
0
0
1
1
PTADD0
PTAPE0
0
0
0
0
89
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