MC9S08AW32CFGE Freescale, MC9S08AW32CFGE Datasheet - Page 91
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MC9S08AW32CFGE
Manufacturer Part Number
MC9S08AW32CFGE
Description
Manufacturer
Freescale
Datasheet
1.MC9S08AW32CFGE.pdf
(324 pages)
Specifications of MC9S08AW32CFGE
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
40MHz
Interface Type
I2C/SCI/SPI
Total Internal Ram Size
2KB
# I/os (max)
34
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
LQFP
Program Memory Type
Flash
Program Memory Size
32KB
Lead Free Status / RoHS Status
Compliant
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6.7.3
Port B parallel I/O function is controlled by the registers listed below.
Freescale Semiconductor
PTBDD[7:0]
PTBD[7:0]
Reset
Reset
Field
Field
7:0
7:0
W
W
R
R
PTBDD7
PTBD7
Port B I/O Registers (PTBD and PTBDD)
Port B Data Register Bits — For port B pins that are inputs, reads return the logic level on the pin. For port B
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port B pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTBD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
Data Direction for Port B Bits — These read/write bits control the direction of port B pins and what is read for
PTBD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn.
0
0
7
7
PTBDD6
PTBD6
0
0
6
6
Figure 6-15. Data Direction for Port B (PTBDD)
Table 6-8. PTBDD Register Field Descriptions
Table 6-7. PTBD Register Field Descriptions
Figure 6-14. Port B Data Register (PTBD)
PTBDD5
PTBD5
0
0
5
5
MC9S08AW60 Data Sheet, Rev 2
PTBDD4
PTBD4
0
0
4
4
Description
Description
PTBDD3
PTBD3
3
0
3
0
PTBDD2
PTBD2
0
0
2
2
Chapter 6 Parallel Input/Output
PTBDD1
PTBD1
0
0
1
1
PTBDD0
PTBD0
0
0
0
0
91
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