MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 243
MCF5272VF66
Manufacturer Part Number
MCF5272VF66
Description
Manufacturer
Freescale
Datasheet
1.MCF5272VF66.pdf
(544 pages)
Specifications of MCF5272VF66
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Lead Free Status / RoHS Status
Not Compliant
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11.5.15 Transmit Control Register (TCR)
The TCR register,
Table 11-22
Freescale Semiconductor
31–3
Bits
2
1
0
Reset
Reset
Field
Field
Addr
R/W
R/W
Name
FDEN
31
15
HBC
GTS
describes the TCR fields.
—
Figure
Reserved, should be cleared.
Full duplex enable. If set, frames are transmitted independent of carrier sense and collision inputs. This
bit should only be modified when ETHER_EN is deasserted.
Heartbeat control. If set, the heartbeat check is performed following end of transmission and the HB
bit in the status register is set if the collision input does not assert within the heartbeat window. This bit
should be modified only when ETHER_EN is deasserted.
Graceful transmit stop. When this bit is set, the MAC stops transmission after any current frame is
complete and the GRA interrupt in the INTR_EVENT register is asserted. If frame transmission is not
currently underway, the GRA interrupt is asserted immediately. Once transmission is complete, a
restart is accomplished by clearing the GTS bit. The next frame in the transmit FIFO is then transmitted.
If an early collision occurs during transmission when GTS = 1, transmission stops after the collision.
The frame is transmitted again once GTS is cleared. Note that there may be old frames in the transmit
FIFO that are transmitted when GTS is reasserted. To avoid this, deassert ETHER_EN following the
GRA interrupt.
MCF5272 ColdFire
11-19, controls the operational mode of the transmit block
Figure 11-19. Transmit Control Register (TCR)
Table 11-22. TCR Field Descriptions
®
Integrated Microprocessor User’s Manual, Rev. 3
—
0000_0000_0000_0000
0000_0000_0000_0000
MBAR + 0x984
Read/Write
Read/Write
—
Description
3
FDEN HBC GTS
2
Ethernet Module
1
16
0
11-25
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