MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 465
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MCF5272VF66
Manufacturer Part Number
MCF5272VF66
Description
Manufacturer
Freescale
Datasheet
1.MCF5272VF66.pdf
(544 pages)
Specifications of MCF5272VF66
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Lead Free Status / RoHS Status
Not Compliant
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20.7
The MCF5272 uses line read transfers to access 16 bytes to support cache line filling DMA transfers, and
MOVEM instructions, when appropriate. A cache line read accesses a block of four longwords, aligned to
a longword memory boundary, by supplying a starting address that points to one of the longwords and
incrementing A[3:0] of the supplied address for each transfer. A longword read accesses a single longword
aligned to a longword boundary and increments A1 and A0 if the accessed port size is smaller than 32 bits.
A word read accesses a single word of data, aligned to a word boundary and increments A0 if the accessed
port size is smaller than 16 bits.
The MCF5272 uses line write transfers to access a 16-byte operand for MOVEM instructions and DMA
transfers, when appropriate. A line write accesses a block of four longwords, aligned to a longword
memory boundary, by supplying a starting address that points to one of the longwords and increments
A[3:0] of the supplied address for each transfer. A longword write accesses a single longword aligned to
a longword boundary and increments A1 and A0 if the accessed port size is smaller than 32 bits. A word
write accesses a single word of data, aligned to a word boundary and increments A0 if the accessed port
size is smaller than 16 bits.
The MCF5272 hardware supports the following types of burst transfers.
Freescale Semiconductor
•
SDCLK
A[22:0]
D[31:0]
OE
R/W
CSn
BS[3:0]
TA
Sixteen byte cache line read bursts from 32-bit wide SDRAM with access times of n-1-1-1. The
value of n depends on read, write, page miss, page hit, etc. See
Burst Data Transfers
(H)
(H)
Figure 20-17. Longword Write with Address Setup and Address Hold;
MCF5272 ColdFire
C1
EBI = 11; 32-Bit Port, Internal Termination
®
Integrated Microprocessor User’s Manual, Rev. 3
C2
C3
C4
Chapter 9, “SDRAM
Controller,”
Bus Operation
20-17
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