MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 69
MCF5272VF66
Manufacturer Part Number
MCF5272VF66
Description
Manufacturer
Freescale
Datasheet
1.MCF5272VF66.pdf
(544 pages)
Specifications of MCF5272VF66
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Lead Free Status / RoHS Status
Not Compliant
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Chapter 2
ColdFire Core
This chapter provides an overview of the microprocessor core of the MCF5272. The chapter describes the
V2 programming model as it is implemented on the MCF5272. It also includes a full description of
exception handling, data formats, an instruction set summary, and a table of instruction timings.
2.1
The MCF5272 is the most highly-integrated V2 standard product, containing a variety of communications
and general-purpose peripherals. The V2 core was designed to maximize code density and performance
while minimizing die area.
The following list summarizes MCF5272 features:
2.1.1
The IFP prefetches instructions. The OEP decodes instructions, fetches required operands, then executes
the specified function. The two independent, decoupled pipeline structures maximize performance while
minimizing core size. Pipeline stages are shown in
Freescale Semiconductor
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Variable-length RISC Version 2 microprocessor core
Two independent, decoupled pipelines—two-stage instruction fetch pipeline (IFP) and two-stage
operand execution pipeline (OEP)
Three longword FIFO buffer provides decoupling between the pipelines
32-bit internal address bus supporting 4 Gbytes of linear address space
32-bit data bus
16 user-accessible, 32-bit-wide, general-purpose registers
Supervisor/user modes for system protection
Vector base register to relocate exception-vector table
Optimized for high-level language constructs
Two-stage IFP (plus optional instruction buffer stage)
— Instruction address generation (IAG) calculates the next prefetch address.
— Instruction fetch cycle (IC) initiates prefetch on the processor’s local instruction bus.
— Instruction buffer (IB) optional stage uses FIFO queue to minimize effects of fetch latency.
Two-stage OEP
— Decode, select/operand fetch (DSOC) decodes the instruction and selects the required
— Address generation/execute (AGEX) calculates the operand address, or performs the execution
Features and Enhancements
components for the effective address calculation, or the operand fetch cycle.
of the instruction.
Decoupled Pipelines
MCF5272 ColdFire
®
Integrated Microprocessor User’s Manual, Rev. 3
Figure 2-1
and are summarized as follows:
2-1
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