MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 476
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MCF5272VF66
Manufacturer Part Number
MCF5272VF66
Description
Manufacturer
Freescale
Datasheet
1.MCF5272VF66.pdf
(544 pages)
Specifications of MCF5272VF66
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Lead Free Status / RoHS Status
Not Compliant
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IEEE 1149.1 Test Access Port (JTAG)
Figure 21-1
21.2
The JTAG test interface shares pins with the debug modules (see
21-2
PSTCLK
Signal
BKPT
TMS/
TDO/
TCK/
DSO
TMS
TCK
TDI
JTAG Test Access Port and BDM Debug Port
Test clock. TCK is the dedicated JTAG test logic clock input, independent of the CPU system clock. It provides a
clock for on-board test logic defined by the IEEE 1149.1 standard. TCK should be grounded if the JTAG port is not
used and MTMOD is tied low.
Test mode select. This input controls test mode operations for on-board test logic defined by the IEEE 1149.1
standard. Connecting TMS to VDD disables the test controller, making all JTAG circuits transparent to the system.
Test and debug data out. Output for shifting data out of serial data port logic. Shifting out data depends on the state
of the JTAG controller state machine and the instructions in the instruction register. The shift occurs on the falling
edge of TCK. When not outputting data, TDO is placed in high-impedance state. TDO can also be three-stated to
allow bused or parallel connections to other devices having JTAG test access ports.
shows the MCF5272 implementation of IEEE 1149.1.
Precautions to ensure that the IEEE 1149.1 test logic does not interfere with
non-test operation are described in
Operation.”
Controller
TAP
MCF5272 ColdFire
3
4-Bit Instruction Register
Figure 21-1. Test Access Port Block Diagram
Boundary-Scan Register
Decoder
Test Data Register
®
Integrated Microprocessor User’s Manual, Rev. 3
Table 21-1. JTAG Signals
ID (32 bits)
Bypass
0
(1 Bit)
NOTE
Section 21.7, “Non-IEEE 1149.1
Description
Table
21-1).
Freescale Semiconductor
TDC
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