MCIMX253CJM4A Freescale, MCIMX253CJM4A Datasheet - Page 50

• Manufacturer Part Number: MCIMX253CJM4A
• Manufacturer: Freescale

Specifications of MCIMX253CJM4A

• Lead Free Status / RoHS Status: Compliant

Figure 17
Timing parameters for UDMA in-burst are listed in
1
Make t
50
Parameter
There is a special timing requirement in the ATA host that requires the internal DIOW to go only high three clocks after the last
active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint.
tdzfs
tzah
ATA
tack
tenv
tcvh
tcyc
tmli
tdh
tds
trp
on
—
—
and t
shows timing for device-terminated UDMA in-transfer.
off
big enough to avoid bus contention.
Parameter
Spec.
tmli1
tdzfs
tdh1
tenv
tds1
tzah
tcvh
tack
tx1
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6
tc1
ton
toff
trp
DATA READ
DATA WRITE
1
DMARQ
DMACK
DIOW
IORDY
ADDR
DIOR
buffer_en
Figure 17. Timing for Device-Terminated UDMA Transfer
tack(min.) = (time_ack
tenv(min.) = (time_env
tenv(max.) = (time_env
tds – (tskew3) – ti_ds > 0
tdh – (tskew3) –ti_dh > 0
(tcyc – tskew) > T
trp(min.) = time_rp
(time_rp
tmli1(min.) = (time_mlix + 0.4)
tzah(min.) = (time_zah + 0.4)
tdzfs = (time_dzfs
tcvh = (time_cvh
ton = time_on
toff = time_off
Table 37. Timing Parameters for UDMA In-Burst
tds
T) – (tco + tsu + 3T + 2
T – tskew1
T – tskew1
tc1
tdh
T) – (tskew1 + tskew2)
T) – (tskew1 + tskew2)
T – (tskew1 + tskew2 + tskew6)
tc1
T) – (tskew1 + tskew2)
T) – (tskew1 + tskew2)
T) + (tskew1 + tskew2)
tss1
Table
T
Value
tli5
T
tbuf + 2
37.
tzah
tzah
tmli
tmli
tcable2) > trfs (drive)
ton tdzfs tcvh
tack
toff
Freescale Semiconductor
Required Conditions
should be low enough
tskew3, ti_ds, ti_dh
T big enough
time_mlix
time_dzfs
time_zah
time_ack
time_env
time_cvh
time_rp
time_rp
—