PCA9306DP-T NXP Semiconductors, PCA9306DP-T Datasheet

PCA9306DP-T

Manufacturer Part Number
PCA9306DP-T
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PCA9306DP-T

Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
TSSOP
Pin Count
8
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
1. General description
The PCA9306 is a dual bidirectional I
enable (EN) input, and is operational from 1.0 V to 3.6 V (V
(V
The PCA9306 allows bidirectional voltage translations between 1.0 V and 5 V without the
use of a direction pin. The low ON-state resistance (R
to be made with minimal propagation delay. When EN is HIGH, the translator switch is on,
and the SCL1 and SDA1 I/O are connected to the SCL2 and SDA2 I/O, respectively,
allowing bidirectional data flow between ports. When EN is LOW, the translator switch is
off, and a high-impedance state exists between ports.
The PCA9306 is not a bus buffer like the PCA9509 or PCA9517A that provide both level
translation and physically isolates the capacitance to either side of the bus when both
sides are connected. The PCA9306 only isolates both sides when the device is disabled
and provides voltage level translation when active.
The PCA9306 can also be used to run two buses, one at 400 kHz operating frequency
and the other at 100 kHz operating frequency. If the two buses are operating at different
frequencies, the 100 kHz bus must be isolated when the 400 kHz operation of the other
bus is required. If the master is running at 400 kHz, the maximum system operating
frequency may be less than 400 kHz because of the delays added by the translator.
As with the standard I
HIGH levels on the translator’s bus. The PCA9306 has a standard open-collector
configuration of the I
but each side of the translator must have a pull-up resistor. The device is designed to work
with Standard-mode, Fast-mode and Fast-mode Plus I
SMBus devices. The maximum frequency is dependent on the RC time constant, but
generally supports > 2 MHz.
When the SDA1 or SDA2 port is LOW, the clamp is in the ON-state and a low resistance
connection exists between the SDA1 and SDA2 ports. Assuming the higher voltage is on
the SDA2 port when the SDA2 port is HIGH, the voltage on the SDA1 port is limited to the
voltage set by VREF1. When the SDA1 port is HIGH, the SDA2 port is pulled to the drain
pull-up supply voltage (V
seamless translation between higher and lower voltages selected by the user without the
need for directional control. The SCL1/SCL2 channel also functions as the SDA1/SDA2
channel.
bias(ref)(2)
PCA9306
Dual bidirectional I
Rev. 6 — 25 November 2010
).
2
C-bus. The size of these pull-up resistors depends on the system,
2
C-bus system, pull-up resistors are required to provide the logic
pu(D)
) by the pull-up resistors. This functionality allows a
2
C-bus and SMBus voltage-level translator
2
C-bus and SMBus voltage-level translator with an
on
2
C-bus devices in addition to
) of the switch allows connections
ref(1)
) and 1.8 V to 5.5 V
Product data sheet

Related parts for PCA9306DP-T

PCA9306DP-T Summary of contents

Page 1

PCA9306 Dual bidirectional I Rev. 6 — 25 November 2010 1. General description The PCA9306 is a dual bidirectional I enable (EN) input, and is operational from 1 3 bias(ref)(2) The PCA9306 allows bidirectional voltage ...

Page 2

... NXP Semiconductors All channels have the same electrical characteristics and there is minimal deviation from one output to another in voltage or propagation delay. This is a benefit over discrete transistor voltage translation solutions, since the fabrication of the switch is symmetrical. The translator provides excellent ESD protection to lower voltage devices, and at the same time protects less ESD-resistant devices ...

Page 3

... +85 C. amb Type number Topside mark PCA9306D PCA9306 PCA9306DP 306P PCA9306DC 306C [2] PCA9306DP1 306T [3] PCA9306DC1 P06 [4] PCA9306GD1 P06 [5] PCA9306GM P6X PCA9306GF 06 [1] Also known as MSOP8. [2] Same footprint and pinout as the Texas Instruments PCA9306DCT. [3] Same footprint and pinout as the Texas Instruments PCA9306DCU. ...

Page 4

... SDA2 002aac372 Pin configuration for SO8 All information provided in this document is subject to legal disclaimers. Rev. 6 — 25 November 2010 PCA9306 2 C-bus and SMBus voltage-level translator 1 GND VREF1 2 PCA9306DP SCL1 3 SDA1 4 002aac373 Fig 3. Pin configuration for TSSOP8 (DP) (MSOP8) GND 1 2 VREF1 PCA9306DC1 ...

Page 5

... NXP Semiconductors GND VREF1 SCL1 SDA1 Fig 8. 5.2 Pin description Table 2. Symbol GND VREF1 SCL1 SDA1 SDA2 SCL2 VREF2 EN PCA9306 Product data sheet Dual bidirectional VREF2 PCA9306GD1 3 6 SCL2 4 5 SDA2 002aae014 Transparent top view Pin configuration for XSON8U (GD1) Pin description ...

Page 6

... NXP Semiconductors 6. Functional description Refer to 6.1 Function table Table HIGH level LOW level. Input [ controlled by the V translator operation. 7. Limiting values Table 4. In accordance with the Absolute Maximum Rating System (IEC 60134). Over operating free-air temperature range. Symbol V ref(1) V bias(ref)( I stg [1] The input and input/output negative voltage ratings may be exceeded if the input and input/output clamp current ratings are observed ...

Page 7

... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics − ° ° +85 C, unless otherwise specified. amb Symbol Parameter V input clamping voltage IK I HIGH-level input current IH C input capacitance on pin EN i(EN) C off-state input/output capacitance io(off) C on-state input/output capacitance io(on) [2] R ON-state resistance °C. ...

Page 8

... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics (translating down) − ° ° +85 C, unless otherwise specified. Values guaranteed by design. amb Symbol Parameter I(EN LOW to HIGH PLH propagation delay t HIGH to LOW PHL propagation delay I(EN LOW to HIGH PLH propagation delay ...

Page 9

... NXP Semiconductors 11. Application information (1) The applied voltages at V Fig 11. Typical application circuit (switch always enabled) (1) In the Enabled mode, the applied enable voltage and the applied voltage at V Fig 12. Typical application circuit (switch enable control) PCA9306 Product data sheet Dual bidirectional I ...

Page 10

... NXP Semiconductors 11.1 Bidirectional translation For the bidirectional clamping configuration (higher voltage to lower voltage or lower voltage to higher voltage), the EN input must be connected to VREF2 and both pins pulled to HIGH side V regulate the EN input. A filter capacitor on VREF2 is recommended. The I output can be totem pole or open-drain (pull-up resistors may be required) and the ...

Page 11

... NXP Semiconductors Table 10. Calculated for V V pu( 3.3 V 2.5 V 1.8 V 1.5 V 1.2 V [1] + compensate for V 11.2.1 Maximum frequency calculation The maximum frequency is totally dependent upon the specifics of the application and the device can operate > 33 MHz. Basically, the PCA9306 behaves like a wire with the additional characteristics of transistor device physics and should be capable of performing at higher frequencies if used correctly ...

Page 12

... NXP Semiconductors 11.2.1.1 Example maximum frequency Question — We need to make the PLL area of a new line card backwards compatible and need to need to convert one GTL signal to LVTTL, invert it, and convert it back to GTL. The signal we want to convert is random in nature but will mostly be around 19 MHz with very long periods of inactivity where either a HIGH or LOW state will be maintained ...

Page 13

... NXP Semiconductors 12. Package outline SO8: plastic small outline package; 8 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 14

... NXP Semiconductors TSSOP8: plastic thin shrink small outline package; 8 leads; body width pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

Page 15

... NXP Semiconductors TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.00 0.75 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. ...

Page 16

... NXP Semiconductors VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0. 0.12 0.00 0.60 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

Page 17

... NXP Semiconductors XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm terminal 1 index area metal area not for soldering 2 1 terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.25 1.65 mm 0.5 0.00 ...

Page 18

... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1. 0.5 mm terminal 1 index area (2) (4× terminal 1 index area Dimensions (1) Unit max 0.5 0.04 0.20 1.40 mm nom 0.15 1.35 min 0.12 1.30 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

Page 19

... NXP Semiconductors XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 0.5 mm terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.35 2.1 mm 0.5 0.00 0.15 1.9 OUTLINE VERSION IEC SOT996 Fig 19. Package outline SOT996-2 (XSON8U) ...

Page 20

... NXP Semiconductors 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...

Page 21

... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...

Page 22

... NXP Semiconductors Fig 20. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 14. Abbreviations Table 13. Acronym CDM ESD GTL HBM 2 I C-bus I/O LVTTL MM PLL PRR RC SMBus PCA9306 Product data sheet ...

Page 23

... NXP Semiconductors 15. Revision history Table 14. Revision history Document ID Release date PCA9306 v.6 20101125 • Modifications: Table 6 “Static non-VSSOP8, XSON8U packages): – Typical value changed from 9.0 Ω Ω – Maximum value changed from 20 Ω Ω – Table note [4] PCA9306 v.5 20100319 PCA9306 v ...

Page 24

... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

Page 25

... PCA9306 Product data sheet Dual bidirectional I own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. ...

Page 26

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 6 6.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 11 Application information ...

Related keywords