IDT82V3001APV IDT, Integrated Device Technology Inc, IDT82V3001APV Datasheet
IDT82V3001APV
Specifications of IDT82V3001APV
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IDT82V3001APV Summary of contents
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FEATURES • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stra- tum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 tim- ing for E1 interface • Selectable input ...
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IDT82V3001A FUNCTIONAL BLOCK DIAGRAM OSCi OSCo OSC Fref FLOCK TDI TMS JTAG TRST TCK TDO RST TIE_en MODE_sel1 FUNCTIONAL BLOCK DIAGRAM TCLR DDA SS DDA SS Virtual TIE Control Reference Block Invalid Input Signal Detection Feedback ...
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IDT82V3001A PIN CONFIGURATION........................................................................................................................... 6 2 PIN DESCRIPTION ........................................................................................................................................................ 7 3 FUNCTIONAL DESCRIPTION..................................................................................................................................... 10 3.1 State Control Circuit............................................................................................................................................. 10 3.1.1 Normal Mode ............................................................................................................................................11 3.1.2 Fast Lock Mode ........................................................................................................................................ 11 3.1.3 Holdover Mode ......................................................................................................................................... 11 3.1.4 Freerun Mode ........................................................................................................................................... 12 3.2 ...
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Figure - 1 Block Diagram .................................................................................................................................................. 2 Figure - 2 IDT82V3001A SSOP56 Package Pin Assignment........................................................................................... 6 Figure - 3 State Control Block......................................................................................................................................... 10 Figure - 4 State Control Diagram.................................................................................................................................... 11 Figure - 5 TIE Control Circuit Diagram ........................................................................................................................... 12 Figure ...
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Table - 1 Pin Description .................................................................................................................................................. 7 Table - 2 Operating Modes and Status...........................................................................................................................10 Table - 3 Input Reference Frequency Selection ............................................................................................................. 12 Table - 4 Absolute Maximum Ratings**.......................................................................................................................... 19 Table - 5 Recommended DC Operating Conditions** .................................................................................................... 19 Table ...
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IDT82V3001A 1 IDT82V3001A PIN CONFIGURATION MODE_sel0 MODE_sel1 TCLR RST Fref F_sel0 F_sel1 V C6o C1.5o C3o C2o V C4o C8o C16o C32o V TCK IDT82V3001A PIN CONFIGURATION ...
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IDT82V3001A 2 PIN DESCRIPTION Table - 1 Pin Description Pin Name Type Number 12, 18, 27, Ground. V Power SS 38 All V 3.3 V Analog Power Supply. V Power 37, 48 DDA Refer to 3.3 V ...
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IDT82V3001A Table - 1 Pin Description (Continued) Pin Name Type Number Clock 32.768 MHz. C32o (CMOS This output is a 32.768 MHz clock used for ST-BUS operation. Clock 16.384 MHz. C16o (CMOS This output is a ...
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IDT82V3001A Table - 1 Pin Description (Continued) Pin Name Type Number 11, Internal Connection 21, 22, 34 Internal Use. These pins should be left open when in normal operation. 35, 43 PIN DESCRIPTION WAN PLL ...
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IDT82V3001A 3 FUNCTIONAL DESCRIPTION The IDT82V3001A is a WAN PLL with single reference input, providing timing (clock) and synchronization (framing) signals to interface circuits for T1 and E1 Primary Rate Digital Transmission links. See Figure - 1. The detail is ...
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IDT82V3001A S1 Normal Mode_sel1=0 Mode_sel0=0 * Note: After reset, Mode_sel1 and Mode_sel0 should be initially set to '10' or '00'. 3.1.1 NORMAL MODE Normal Mode is typically used when a slave clock source synchronized to the network is required. In ...
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IDT82V3001A 3.1.4 FREERUN MODE Freerun Mode is typically used when a master clock source is required system is just powered up and the network synchronization has not been achieved. In Freerun Mode, the IDT82V3001A provides timing and synchronization ...
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IDT82V3001A Previous Fref Current Fref Time = 0.00 s Time = 0.25 s Time = 0.50 s Time = 0.75 s Time = 1.0 s Time = 1.25 s Time = 1.50 s Time = 1.75 s The phase difference ...
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IDT82V3001A 3.5 DPLL BLOCK As shown in Figure - 8, the DPLL Block consists of a Phase Detector, a Limiter, a Loop Filter, a Digital Control Oscillator and Dividers. Fraction_T1 Fraction_C6 Loop Filter 3.5.1 PHASE DETECTOR (PHD) In Normal Mode, ...
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IDT82V3001A 3.5.4 FRACTION BLOCK By applying some algorithms to the incoming E1 signal, the Fraction_C6 and Fraction_T1 blocks generate C6 and T1 signals respectively. 3.5.5 DIGITAL CONTROL OSCILLATOR (DCO) In Normal Mode, the DCO receives three limited and filtered signals ...
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IDT82V3001A 3.9 POWER SUPPLY FILTERING TECHNIQUES To achieve optimum jitter performance, power supply filtering is required to minimize supply noise modulation of the output clocks. The common sources of power supply noise are switching power supplies and the high switching ...
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IDT82V3001A 4 MEASURES OF MANCE The following are some synchronizer performance indicators and their corresponding definitions. 4.1 INTRINSIC JITTER Intrinsic jitter is the jitter produced by the synchronizing circuit and is measured at its output measured by applying ...
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IDT82V3001A observation period is usually the time from the disturbance, to just after the synchronizer has settled to a steady state. In the case of the IDT82V3001A, the output signal phase continuity is maintained to within ± the ...
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IDT82V3001A 5 TEST SPECIFICATIONS ** Table - 4 Absolute Maximum Ratings Rating Power Supply Voltage Voltage on Any Pin with Respect to Ground Package Power Dissipation Storage Temperature Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause ...
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IDT82V3001A 5.1 AC ELECTRICAL CHARACTERISTICS Table - 7 Performance Description Freerun Mode accuracy with OSCi ppm Freerun Mode accuracy with OSCi at : ±32 ppm Freerun Mode accuracy with OSCi at : ±100 ppm Holdover Mode accuracy ...
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IDT82V3001A Table - 9 C1.5o (1.544 MHz) Intrinsic Jitter Filtered Description Intrinsic jitter ( 100 kHz filter) Intrinsic jitter ( kHz filter) Intrinsic jitter (8 kHz to 40 kHz filter) Intrinsic jitter ( ...
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IDT82V3001A Table - 13 2.048 MHz Input to 2.048 MHz Output Jitter Transfer Description Jitter at output for 1 Hz@3.00 UIpp input Jitter at output for 1 Hz@3.00 UIpp input with 100 Hz filter Jitter at output ...
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IDT82V3001A Table - 16 2.048 MHz Input Jitter Tolerance Description Jitter tolerance for 1 Hz input Jitter tolerance for 5 Hz input Jitter tolerance for 20 Hz input Jitter tolerance for 300 Hz input Jitter tolerance for 400 Hz input ...
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IDT82V3001A 6 TIMING CHARACTERISTICS Table - 17 Timing Parameter Measurement Voltage Levels Parameter Rise and Fall Threshold Voltage High HM V Rise and Fall Threshold Voltage Low LM Notes: 1. Voltages are with respect to ground (V ...
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IDT82V3001A Table - 18 Input / Output Timing (Continued) Parameter Description t C2o pulse width high or low C2W t C4o pulse width high or low C4W t C8o pulse width high or low C8W t C16o pulse width high ...
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IDT82V3001A F8o F0o F16o F32o C32o C16o C8o t C4W C4o C2o t C6W C6o C3o C1.5o TIMING CHARACTERISTICS t F0WL t F16WL t F16S t F32WL t F32S t C32WH t C16WL t t C8W C8W t C4W t ...
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IDT82V3001A F8o C2o RSP TSP F8o MODE_sel0 MODE_sel1 TIE_en TIMING CHARACTERISTICS t RSPD t TSPW t TSPD Figure - 14 Output Timing Figure - 15 Input Control Setup and Hold Timing 27 WAN PLL WITH ...
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IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT 7 ORDERING INFORMATION XXXXXXXX Device Type Package DATASHEET DOCUMENT HISTORY 10/22/2003 pgs. 7, 23, 24 11/18/2004 pgs 10/15/2008 pgs. 28 removed "IDT" from the orderable part number. 05/24/2006 pgs ...