SSTUH32865ET NXP Semiconductors, SSTUH32865ET Datasheet - Page 17

• Manufacturer Part Number: SSTUH32865ET
• Manufacturer: NXP Semiconductors

Specifications of SSTUH32865ET

• Logic Family: SSTU
• Logical Function: Reg Bfr W/ParityTst
• Number Of Elements: 1
• Number Of Bits: 28
• Number Of Inputs: 28
• Number Of Outputs: 56
• High Level Output Current: -12mA
• Low Level Output Current: 12mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 450(Min)MHz
• Mounting: Surface Mount
• Pin Count: 160
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Table 9:
Over recommended operating conditions, unless otherwise noted.
[1]
[2]
[3]
Table 10:
Over recommended operating conditions, unless otherwise noted.
[1]
[2]
Table 11:
Over recommended operating conditions, unless otherwise noted.
9397 750 14136
Product data sheet
Symbol
f
t
t
t
t
t
Symbol
f
t
t
t
t
t
t
Symbol
dV/dt_r
dV/dt_f
dV/dt_
clock
W
ACT
INACT
su
h
MAX
PDM
LH
HL
PLH
PDMSS
PHL
This parameter is not necessarily production tested.
Data inputs must be active below a minimum time of t
Data and clock inputs must be held at valid levels (not floating) a minimum time of t
Includes 350 ps of test-load transmission line delay.
This parameter is not necessarily production tested.
Timing requirements
Switching characteristics
Output edge rates
Parameter
clock frequency
pulse duration, CK, CK HIGH or
LOW
differential inputs active time
differential inputs inactive time
setup time, Chip Select
setup time, Data
setup time, PARIN
hold time
hold time, PARIN
Parameter
maximum input clock frequency
propagation delay
LOW-to-HIGH delay
HIGH-to-LOW delay
LOW-to-HIGH propagation delay
propagation delay, simultaneous
switching
propagation delay
Parameter
rising edge slew rate
falling edge slew rate
absolute difference between dV/dt_r
and dV/dt_f
Rev. 01 — 11 March 2005
Conditions
DCS0, DCS1 valid before
clock switching
Dn valid before clock
switching
PARIN before CK and CK
input to remain valid after
clock switching
PARIN after CK and CK
Conditions
CK and CK to output
CK and CK to PTYERR
CK and CK to PTYERR
from RESET to PTYERR
CK and CK to output
RESET to output
Conditions
ACT(max)
1.8 V high output drive DDR registered buffer with parity
after RESET is taken HIGH.
INACT(max)
[1] [2]
[1] [3]
[1] [2]
[1]
after RESET is taken LOW.
Min
-
1
-
-
0.7
0.5
0.5
0.5
0.5
Min
450
1.41
1.2
1
-
-
-
Min
1
1
-
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SSTUH32865
Typ
-
-
-
-
-
-
-
-
-
Typ
-
-
-
-
-
-
-
Typ
-
-
-
Max
450
-
10
15
-
-
-
-
-
Max
-
1.8
3
3
3
2.0
3
Max
4
4
1
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Unit
MHz
ns
ns
ns
ns
ns
ns
Unit
V/ns
V/ns
V/ns
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