IDT74FCT162260CTPA IDT, Integrated Device Technology Inc, IDT74FCT162260CTPA Datasheet - Page 3

• Manufacturer Part Number: IDT74FCT162260CTPA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT74FCT162260CTPA

• Lead Free Status / RoHS Status: Not Compliant

IDT54/74FCT16260AT/CT/ET, 162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
PIN DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
CAPACITANCE
NOTE:
1. This parameter is measured at characterization but not tested.
Symbol
V
V
T
I
Symbol
C
C
OUT
STG
1B
2B
TERM (2)
TERM (3)
LEA1B
LEA2B
Signal
IN
I/O
A
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied.
extended periods may affect reliability.
OE1B
OE2B
LE1B
LE2B
OEA
SEL
(1:12)
(1:12)
(1:12
)
Terminal Voltage with Respect to
GND
Terminal Voltage with Respect to
GND
Storage Temperature
DC Output Current
Input
Capacitance
I/O
Capacitance
Parameter
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
Exposure to absolute maximum rating conditions for
Description
(T
Bidirectional Data Port A. Usually connected to the CPU's Address/Data bus.
Bidirectional Data Port 1B. Connected to the even path or even bank of memory.
Bidirectional Data Port 2B. Connected to the odd path or odd bank of memory.
Latch Enable Input for A-1B Latch. The Latch is open when LEA1B is HIGH. Data from the A-port is latched on
the HIGH to LOW transition of LEA1B.
Latch Enable Input for A-2B Latch. The Latch is open when LEA2B is HIGH. Data from the A-Port is latched on
the HIGH to LOW transition of LEA2B.
Latch Enable Input for the 1B-A Latch. The Latch is open when LE1B is HIGH. Data from the 1B port is latched
on the HIGH to LOW transition of LE1B.
Latch Enable Input for the 2B-A Latch. The Latch is open when LE2B is HIGH. Data from the 2B port is latched
on the HIGH to LOW transition of LE2B.
1B or 2B Path Selection. When HIGH, SEL enables data transfer from 1B Port to A Port. When LOW, SEL enables
data transfer from 2B Port to A Port.
Output Enable for A Port (Active LOW).
Output Enable for 1B Port (Active LOW).
Output Enable for 2B Port (Active LOW).
(1)
A
= +25 C, F = 1.0MH
Conditions
V
V
OUT
IN
= 0V
= 0V
(1)
–0.5 to +7.0
–65 to +150
–60 to +120
Typ.
V
3.5
3.5
–0.5 to
CC
Z
Max.
)
+0.5
Max. Unit
6.0
8.0
3032 tbl 02
3032 tbl 03
Unit
mA
V
V
C
pF
pF
5.4
FUNCTION TABLES
NOTES:
1. Output level before the indicated steady-state input conditions were
2. H = HIGH Voltage Level
Description
1B
established.
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
A
H
H
H
X
X
X
X
X
H
X
X
X
X
X
L
L
L
L
= LOW-to-HIGH Transition
LEA1B LEA2B
2B
MILITARY AND COMMERCIAL TEMPERATURES RANGES
H
H
H
H
X
X
X
X
X
X
X
H
X
X
L
L
L
L
Inputs
SEL
H
H
H
H
X
X
X
X
H
H
H
X
L
L
L
L
L
L
Inputs
OE1B
OE1B OE2B
LE1B LE2B
H
H
H
H
X
X
X
X
L
L
L
L
L
L
L
L
L
L
(2)
OE2B
H
H
X
X
X
H
H
X
L
L
L
L
L
L
L
L
L
L
OEA
OEA
Active
Active
H
L
L
L
L
L
L
B
B
B
1B
H
L
H
L
Z
Z
(1)
(1)
(1)
Outputs
Output
A
A
Active
Active
A
H
H
L
L
Z
(1)
(1)
3032 tbl 01
B
B
B
2B
H
L
H
L
Z
Z
3032 tbl 04
3032 tbl 05
(1)
(1)
(1)
3