RC82545EM 845633 Intel, RC82545EM 845633 Datasheet - Page 23
RC82545EM 845633
Manufacturer Part Number
RC82545EM 845633
Description
Manufacturer
Intel
Datasheet
1.RC82545EM_845633.pdf
(54 pages)
Specifications of RC82545EM 845633
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4.0
4.1
4.1.1
Datasheet
Figure 2. XOR Tree Concept
Test Port Functionality
XOR Testing
A common board or system-level manufacturing test for proper electrical continuity between a
silicon component and the board is some type of cascaded-XOR or NAND tree test. The 82545EM
implements an XOR tree spanning most I/O signals. The component XOR tree consists of a series
of cascaded XOR logic gates, each stage feeding in the electrical value from a unique pin. The
output of the final stage of the tree is visible on an output pin from the component.
By connecting to a set of test-points or bed-of-nails fixture, a manufacturing test fixture can test
connectivity to each of the component pins included in the tree by sequentially testing each pin,
testing each pin when driven both high and low, and observing the output of the tree for the
expected signal value and/or change.
XOR Tree Control and Operation
The following signals are required to place the 82545EM in XOR tree test mode:
Function/
XOR Tree
Test
Mode
Test
Dual-Mode
Name
Pin Name
0
TEST_DM_N
TEST_
MODE[3]
0
EWRAP
TEST_
MODE[2]
0
CLK_BYP_N
Networking Silicon — 82545EM
TEST_
MODE[1]
0
CLK_VIEW
TEST_
MODE[0]
0
SDP_B[7]
19
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