MT49H16M36BM-25IT:A Micron Technology Inc, MT49H16M36BM-25IT:A Datasheet - Page 62

• Manufacturer Part Number: MT49H16M36BM-25IT:A
• Manufacturer: Micron Technology Inc
• Type: RLDRAMr

Specifications of MT49H16M36BM-25IT:A

• Organization: 16Mx36
• Address Bus: 23b
• Operating Supply Voltage (typ): 1.8V
• Package Type: uBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Configuration Tables in Multiplexed Address Mode
Table 23:
REFRESH Command in Multiplexed Address Mode
Figure 38:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN
COMMAND
Valid frequency range
ADDRESS
BANK
CK#
CK
Parameter
t
t
t
WL
RC
RL
Bank n
AC
T0
Ax
Cycle Time and READ/WRITE Latency Configuration Table in Multiplexed Mode
Notes 1–2 apply to the entire table
1
BURST REFRESH Operation with Multiplexed Addressing
Notes:
Notes:
NOP
T1
Ay
In multiplexed address mode, the read and write latencies are increased by one clock
cycle. However, the RLDRAM cycle time remains the same as when in non-multiplexed
address mode.
1.
2. Minimum operating frequency for -18 is 370 MHz.
3. BL = 8 is not available.
4. The minimum
Similar to other commands when in multiplexed address mode, AREF is executed on the
rising clock edge following the one on which the command is issued. However, since
only the bank address is required for AREF, the next command can be applied on the
following clock. The operation of the AREF command and any other command is repre-
sented in Figure 38 on page 62.
1. Any command.
2. Bank n is chosen so that
266–175
Bank 0
AREF
t
the same bank. In this instance the minimum
T2
RC <20ns in any configuration is only available with -25E and -18 speed grades.
1
4
5
6
3
576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II
Bank 1
AREF
T3
t
RC is typically 3 cycles, except in the case of a WRITE followed by a READ to
400–175
Bank 2
T4
AREF
2
6
7
8
t
RC is met.
Bank 3
AREF
T5
62
Configuration
533–175
10
3
8
9
Bank 4
AREF
T6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RC is 4 cycles.
Bank 5
T7
AREF
200–175
4
3, 4
3
4
5
Bank 6
T8
AREF
©2004 Micron Technology, Inc. All rights reserved.
Bank 7
T9
AREF
333–175
5
5
6
7
T10
Bank n
AC
Ax
Operations
1
DON’T CARE
Units
MHz
T11
t
t
t
CK
CK
CK
Ay