MT49H16M36BM-25IT:A Micron Technology Inc, MT49H16M36BM-25IT:A Datasheet - Page 68

• Manufacturer Part Number: MT49H16M36BM-25IT:A
• Manufacturer: Micron Technology Inc
• Type: RLDRAMr

Specifications of MT49H16M36BM-25IT:A

• Organization: 16Mx36
• Address Bus: 23b
• Operating Supply Voltage (typ): 1.8V
• Package Type: uBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Test Data-In (TDI)
Test Data-Out (TDO)
TAP Controller
Test-Logic-Reset
Run-Test/Idle
Select-DR-Scan
Capture-DR
Shift-DR
Exit1-DR, Pause-DR, and Exit2-DR
PDF: 09005aef80a41b46/Source: 09005aef809f284b
RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN
The TDI ball is used to serially input test instructions and data into the registers and can
be connected to the input of any of the registers. The register between TDI and TDO is
chosen by the instruction that is loaded into the TAP instruction register. For informa-
tion on loading the instruction register, see Figure 43 on page 69. TDI is connected to the
most significant bit (MSB) of any register (see Figure 44 on page 69).
The TDO output ball is used to serially clock test instructions and data out from the
registers. The TDO output driver is only active during the Shift-IR and Shift-DR TAP
controller states. In all other states, the TDO pin is in a High-Z state. The output changes
on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any
register (see Figure 44 on page 69).
The TAP controller is a finite state machine that uses the state of the TMS pin at the
rising edge of TCK to navigate through its various modes of operation. The TAP
controller state diagram can be seen in Figure 43 on page 69. Each state is described in
detail below.
The test-logic-reset controller state is entered when TMS is held HIGH for at least five
consecutive rising edges of TCK. As long as TMS remains HIGH, the TAP controller will
remain in the test-logic-reset state. The test logic is inactive during this state.
The run-test/idle is a controller state in between scan operations. This state can be
maintained by holding TMS LOW. From here either the data register scan, or subse-
quently, the instruction register scan can be selected.
Select-DR-scan is a temporary controller state. All test data registers retain their previous
state while here.
The capture-DR state is where the data is parallel-loaded into the test data registers. If
the boundary scan register is the currently selected register, then the data currently on
the pins is latched into the test data registers.
Data is shifted serially through the data register while in this state. As new data is input
through the TDI pin, data is shifted out of the TDO pin.
The purpose of exit1-DR is used to provide a path to return back to the run-test/idle
state (through the update-DR state). The pause-DR state is entered when the shifting of
data through the test registers needs to be suspended. When shifting is to reconvene, the
controller enters the exit2-DR state and then can re-enter the shift-DR state.
576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II
68
IEEE 1149.1 Serial Boundary Scan (JTAG)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.