MT47H128M16HG-37E:A Micron Technology Inc, MT47H128M16HG-37E:A Datasheet - Page 7

• Manufacturer Part Number: MT47H128M16HG-37E:A
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H128M16HG-37E:A

• Organization: 128Mx16
• Address Bus: 17b
• Access Time (max): 500ps
• Maximum Clock Rate: 533MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 195mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

List of Figures
Figure 1: 2Gb DDR2 Part Numbers ................................................................................................................... 2
Figure 2: Simplified State Diagram ................................................................................................................... 9
Figure 3: Functional Block Diagram – 512 Meg x 4 .......................................................................................... 12
Figure 4: Functional Block Diagram – 256 Meg x 8 .......................................................................................... 13
Figure 5: Functional Block Diagram – 128 Meg x 16 ........................................................................................ 14
Figure 6: 60-Ball FBGA – x4, x8 Ball Assignments (Top View) ........................................................................... 15
Figure 7: 84-Ball FBGA – x16 Ball Assignments (Top View) .............................................................................. 16
Figure 8: 84-Ball FBGA Package (11.5mm x 14mm) – x16 ................................................................................. 19
Figure 9: 84-Ball FBGA Package (9mm x 12.5mm) – x16 ................................................................................... 20
Figure 10: 60-Ball FBGA Package (11.5mm x 14mm) – x4, x8 ............................................................................ 21
Figure 11: 60-Ball FBGA Package (9mm x 11.5mm) – x4, x8 .............................................................................. 22
Figure 12: Example Temperature Test Point Location ..................................................................................... 25
Figure 13: Single-Ended Input Signal Levels ................................................................................................... 46
Figure 14: Differential Input Signal Levels ...................................................................................................... 47
Figure 15: Differential Output Signal Levels .................................................................................................... 49
Figure 16: Output Slew Rate Load .................................................................................................................. 50
Figure 17: Full Strength Pull-Down Characteristics ......................................................................................... 51
Figure 18: Full Strength Pull-Up Characteristics ............................................................................................. 52
Figure 19: Reduced Strength Pull-Down Characteristics ................................................................................. 53
Figure 20: Reduced Strength Pull-Up Characteristics ...................................................................................... 54
Figure 21: Input Clamp Characteristics .......................................................................................................... 55
Figure 22: Overshoot ..................................................................................................................................... 56
Figure 23: Undershoot .................................................................................................................................. 56
Figure 24: Nominal Slew Rate for
Figure 25: Tangent Line for
Figure 26: Nominal Slew Rate for
Figure 27: Tangent Line for
Figure 28: Nominal Slew Rate for
Figure 29: Tangent Line for
Figure 30: Nominal Slew Rate for
Figure 31: Tangent Line for
Figure 32: AC Input Test Signal Waveform Command/Address Balls ............................................................... 69
Figure 33: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential) ........................................... 69
Figure 34: AC Input Test Signal Waveform for Data with DQS (Single-Ended) .................................................. 70
Figure 35: AC Input Test Signal Waveform (Differential) ................................................................................. 70
Figure 36: MR Definition ............................................................................................................................... 78
Figure 37: CL ................................................................................................................................................ 81
Figure 38: EMR Definition ............................................................................................................................. 82
Figure 39: READ Latency ............................................................................................................................... 85
Figure 40: WRITE Latency ............................................................................................................................. 85
Figure 41: EMR2 Definition ........................................................................................................................... 86
Figure 42: EMR3 Definition ........................................................................................................................... 87
Figure 43: DDR2 Power-Up and Initialization ................................................................................................. 88
Figure 44: Example: Meeting
Figure 45: Multibank Activate Restriction ....................................................................................................... 92
Figure 46: READ Latency ............................................................................................................................... 94
Figure 47: Consecutive READ Bursts .............................................................................................................. 95
Figure 48: Nonconsecutive READ Bursts ........................................................................................................ 96
Figure 49: READ Interrupted by READ ........................................................................................................... 97
Figure 50: READ-to-WRITE ............................................................................................................................ 97
PDF: 09005aef824f87b6
2gbddr2.pdf – Rev. F 12/10 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
2Gb: x4, x8, x16 DDR2 SDRAM
© 2006 Micron Technology, Inc. All rights reserved.
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