CBTV4020EE NXP Semiconductors, CBTV4020EE Datasheet
CBTV4020EE
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CBTV4020EE Summary of contents
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CBTV4020 20-bit DDR SDRAM MUX Rev. 03 — 4 April 2008 1. General description This 20-bit bus switch is designed for 2 2 input levels. Each host port pin is multiplexed to one ...
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... Capacitance values are measured at 10 MHz and a bias voltage 3 V. Capacitance is not production tested. 4. Ordering information Table 2. Ordering information +85 C amb Type number Package Name CBTV4020EE/G TFBGA72 5. Functional diagram Fig 1. CBTV4020_3 Product data sheet Conditions from input DHn or DAn/DBn to output DAn/DBn or DHn ...
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... DA1 DH1 H DB1 DH2 DH3 DB3 J DA2 DB2 DA3 DA4 K Transparent top view. Empty cell indicates no ball present at that location. TFBGA72 ball mapping Rev. 03 — 4 April 2008 CBTV4020 20-bit DDR SDRAM MUX CBTV4020EE 002aad695 Transparent top view DA15 DB14 DA14 DA13 ...
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... NXP Semiconductors 6.2 Pin description Table 3. Symbol DH0 DH1 DH2 DH3 DH4 DH5 DH6 DH7 DH8 DH9 DH10 DH11 DH12 DH13 DH14 DH15 DH16 DH17 DH18 DH19 SEL GND V DD DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 ...
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... NXP Semiconductors Table 3. Symbol DA16 DA17 DA18 DA19 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DB16 DB17 DB18 DB19 7. Functional description Refer to 7.1 Function selection Table HIGH voltage level LOW voltage level. ...
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... NXP Semiconductors 8. Limiting values Table 5. In accordance with the Absolute Maximum Rating System (IEC 60134). The package thermal impedance is calculated in accordance with JESD 51. Symbol stg [1] The input and output negative voltage ratings may be exceeded if the input and output clamping current ratings are observed. ...
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... NXP Semiconductors 10. Static characteristics Table 7. Static characteristics +85 C. amb Symbol Parameter V input clamping current IK I input leakage current LI I supply current DD I LOW-level output current OL C control pin capacitance in C switch on capacitance resistance ON R pull-down resistance pd [1] All typical values are ...
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... NXP Semiconductors 11.1 DHn to DAn/DBn AC waveforms input 1. PLH output 1.25 V Fig 4. Input to output propagation delays 11.2 DAn/DBn to DHn AC waveforms (1) The output is LOW except when disabled by the SEL control. (2) The output is HIGH except when disabled by the SEL control. Fig 6. Output enable and disable times ...
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... NXP Semiconductors 12. Test information All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z The outputs are measured one at a time with one transition per measurement load capacitance; includes jig and probe capacitance. L Fig 9. Fig 10. Test circuit, DAn/DBn to DHn Table 9 ...
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... NXP Semiconductors 13. Package outline TFBGA72: plastic thin fine-pitch ball grid array package; 72 balls; body 0.8 mm ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) A UNIT max. 0.25 0.85 0.35 mm 1.1 0.15 0.75 0.25 OUTLINE VERSION IEC SOT761 Fig 11. Package outline SOT761-1 (TFBGA72) ...
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... NXP Semiconductors 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 12. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 15. Abbreviations Table 12. Acronym CDM DDR DIMM ESD HBM MM PRR RC SDRAM SSTL_2 CBTV4020_3 Product data sheet ...
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... Table 8 “Dynamic characteristics”) information”: deleted type number CBTV4020EE Figure 2 “Pin configuration for TFBGA72” description”: expanded to detail pin assignments values”: : changed “S pin” to “SEL pin” ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 5 7.1 Function selection Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 11.1 DHn to DAn/DBn AC waveforms ...