LFXP2-5E-5FT256I LATTICE SEMICONDUCTOR, LFXP2-5E-5FT256I Datasheet - Page 29

• Manufacturer Part Number: LFXP2-5E-5FT256I
• Description: FPGA LatticeXP2 Family 5000 Cells Flash Technology 1.2V 256-Pin FTBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFXP2-5E-5FT256I

• Package: 256FTBGA
• Family Name: LatticeXP2
• Device Logic Units: 5000
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 172
• Ram Bits: 169984
• Re-programmability Support: Yes

Lattice Semiconductor
Programmable I/O Cells (PIC)
Each PIC contains two PIOs connected to their respective sysIO buffers as shown in Figure 2-25. The PIO Block
supplies the output data (DO) and the tri-state control signal (TO) to the sysIO buffer and receives input from the
buffer. Table 2-11 provides the PIO signal list.
Figure 2-25. PIC Diagram
Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”) as shown in Figure 2-25.
The PAD Labels “T” and “C” distinguish the two PIOs. Approximately 50% of the PIO pairs on the left and right
edges of the device can be configured as true LVDS outputs. All I/O pairs can operate as inputs.
DDRCLKPOL
1. Signals are available on left/right/bottom edges only.
2. Selected blocks.
DQSXFER
ONEG2
QNEG0
QNEG1
OPOS2
QPOS0
QPOS1
OPOS1
ONEG1
OPOS0
ONEG0
ECLK1
ECLK2
IPOS0
IPOS1
GSRN
INCK
INDD
INFF
DQS
CLK
LSR
DEL
CE
TD
1
1
1
1
1
1
2
1
1
Control
Muxes
CLK1
CLK0
CEO
GSR
LSR
CEI
2-26
PIOA
Register
Register
Register
Tristate
Output
Block
Block
Block
Input
PIOB
IOLD0
IOLT0
DI
LatticeXP2 Family Data Sheet
Buffer
sysIO
PADB
PADA
“C”
“T”
Architecture