LFXP2-5E-5FT256I LATTICE SEMICONDUCTOR, LFXP2-5E-5FT256I Datasheet - Page 7

• Manufacturer Part Number: LFXP2-5E-5FT256I
• Description: FPGA LatticeXP2 Family 5000 Cells Flash Technology 1.2V 256-Pin FTBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFXP2-5E-5FT256I

• Package: 256FTBGA
• Family Name: LatticeXP2
• Device Logic Units: 5000
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 172
• Ram Bits: 169984
• Re-programmability Support: Yes

Lattice Semiconductor
Figure 2-3. Slice Diagram
Table 2-2. Slice Signal Descriptions
1. See Figure 2-3 for connection details.
2. Requires two PFUs.
Function
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Routing
From
Inter-PFU signal
Inter-slice signal
Inter-slice signal
Inter-PFU signal
Multi-purpose
Multi-purpose
Control signal
Control signal
Control signal
Data signals
Data signals
Data signals
Data signals
Data signal
Data signal
FXB
FXA
CLK
LSR
Type
M1
M0
CE
A1
B1
C1
D1
A0
B0
C0
D0
* Not in Slice 3
For Slices 0 and 2, memory control signals are generated from Slice 1 as follows:
WCK is CLK
WRE is from LSR
DI[3:2] for Slice 2 and DI[1:0] for Slice 0 data
WAD [A:D] is a 4bit address from slice 1 LUT input
FCO from Slice/PFU, FCI into Different Slice/PFU
A0, B0, C0, D0
A1, B1, C1, D1
Signal Names
Q0, Q1
F0, F1
OFX0
OFX1
FCO
LSR
CLK
FXA
FXB
FCI
M0
M1
CE
FCI into Slice/PFU, FCO from Different Slice/PFU
LUT4 &
CARRY*
LUT4 &
CARRY*
Inputs to LUT4
Inputs to LUT4
Multipurpose Input
Multipurpose Input
Clock Enable
Local Set/Reset
System Clock
Fast Carry-In
Intermediate signal to generate LUT6 and LUT7
Intermediate signal to generate LUT6 and LUT7
LUT4 output register bypass signals
Register outputs
Output of a LUT5 MUX
Output of a LUT6, LUT7, LUT8
Slice 2 of each PFU is the fast carry chain output
CO
CO
CI
CI
2-4
F/SUM
F/SUM
1
LUT5
Mux
Description
LatticeXP2 Family Data Sheet
2
MUX depending on the slice
SLICE
D
D
FF*
FF*
Routing
OFX1
F1
Q1
To
OFX0
F0
Q0
1
Architecture