LFXP2-5E-5FT256I LATTICE SEMICONDUCTOR, LFXP2-5E-5FT256I Datasheet - Page 8

• Manufacturer Part Number: LFXP2-5E-5FT256I
• Description: FPGA LatticeXP2 Family 5000 Cells Flash Technology 1.2V 256-Pin FTBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFXP2-5E-5FT256I

• Package: 256FTBGA
• Family Name: LatticeXP2
• Device Logic Units: 5000
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 172
• Ram Bits: 169984
• Re-programmability Support: Yes

Lattice Semiconductor
Modes of Operation
Each slice has up to four potential modes of operation: Logic, Ripple, RAM and ROM.
Logic Mode
In this mode, the LUTs in each slice are configured as LUT4s. A LUT4 has 16 possible input combinations. Four-
input logic functions are generated by programming the LUT4. Since there are two LUT4s per slice, a LUT5 can be
constructed within one slice. Larger LUTs such as LUT6, LUT7 and LUT8, can be constructed by concatenating
two or more slices. Note that a LUT8 requires more than four slices.
Ripple Mode
Ripple mode allows efficient implementation of small arithmetic functions. In ripple mode, the following functions
can be implemented by each slice:
• Addition 2-bit
• Subtraction 2-bit
• Add/Subtract 2-bit using dynamic control
• Up counter 2-bit
• Down counter 2-bit
• Up/Down counter with async clear
• Up/Down counter with preload (sync)
• Ripple mode multiplier building block
• Multiplier support
• Comparator functions of A and B inputs
Two carry signals, FCI and FCO, are generated per slice in this mode, allowing fast arithmetic functions to be con-
structed by concatenating slices.
RAM Mode
In this mode, a 16x4-bit distributed Single Port RAM (SPR) can be constructed using each LUT block in Slice 0 and
Slice 2 as a 16x1-bit memory. Slice 1 is used to provide memory address and control signals. A 16x2-bit Pseudo
Dual Port RAM (PDPR) memory is created by using one slice as the read-write port and the other companion slice
as the read-only port.
The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft-
ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3
shows the number of slices required to implement different distributed RAM primitives. For more information on
using RAM in LatticeXP2 devices, please see TN1137,
Table 2-3. Number of Slices Required For Implementing Distributed RAM
ROM Mode
ROM mode uses the LUT logic; hence, Slices 0 through 3 can be used in the ROM mode. Preloading is accom-
plished through the programming interface during PFU configuration.
– A greater-than-or-equal-to B
– A not-equal-to B
– A less-than-or-equal-to B
Number of slices
Note: SPR = Single Port RAM, PDPR = Pseudo Dual Port RAM
SPR 16X4
LatticeXP2 Memory Usage
2-5
3
LatticeXP2 Family Data Sheet
Guide.
PDPR 16X4
3
Architecture