LFXP2-5E-5FT256I LATTICE SEMICONDUCTOR, LFXP2-5E-5FT256I Datasheet - Page 9

• Manufacturer Part Number: LFXP2-5E-5FT256I
• Description: FPGA LatticeXP2 Family 5000 Cells Flash Technology 1.2V 256-Pin FTBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFXP2-5E-5FT256I

• Package: 256FTBGA
• Family Name: LatticeXP2
• Device Logic Units: 5000
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 172
• Ram Bits: 169984
• Re-programmability Support: Yes

Architecture
Lattice Semiconductor
LatticeXP2 Family Data Sheet
Routing
There are many resources provided in the LatticeXP2 devices to route signals individually or as busses with related
control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) seg-
ments.
The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) or x6 (spans seven PFU)
connections. The x1 and x2 connections provide fast and efficient connections in horizontal and vertical directions.
The x2 and x6 resources are buffered to allow both short and long connections routing between PFUs.
The LatticeXP2 family has an enhanced routing architecture to produce a compact design. The ispLEVER design
tool takes the output of the synthesis tool and places and routes the design. Generally, the place and route tool is
completely automatic, although an interactive routing editor is available to optimize the design.
sysCLOCK Phase Locked Loops (PLL)
The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The LatticeXP2 family supports between
two and four full featured General Purpose PLLs (GPLL). The architecture of the GPLL is shown in Figure 2-4.
CLKI, the PLL reference frequency, is provided either from the pin or from routing; it feeds into the Input Clock
Divider block. CLKFB, the feedback signal, is generated from CLKOP (the primary clock output) or from a user
clock pin/logic. CLKFB feeds into the Feedback Divider and is used to multiply the reference frequency.
Both the input path and feedback signals enter the Voltage Controlled Oscillator (VCO) block. The phase and fre-
quency of the VCO are determined from the input path and feedback signals. A LOCK signal is generated by the
VCO to indicate that the VCO is locked with the input clock signal.
The output of the VCO feeds into the CLKOP Divider, a post-scalar divider. The duty cycle of the CLKOP Divider
output can be fine tuned using the Duty Trim block, which creates the CLKOP signal. By allowing the VCO to oper-
ate at higher frequencies than CLKOP, the frequency range of the GPLL is expanded. The output of the CLKOP
Divider is passed through the CLKOK Divider, a secondary clock divider, to generate lower frequencies for the
CLKOK output. For applications that require even lower frequencies, the CLKOP signal is passed through a divide-
by-three divider to produce the CLKOK2 output. The CLKOK2 output is provided for applications that use source
synchronous logic. The Phase/Duty Cycle/Duty Trim block is used to adjust the phase and duty cycle of the CLKOP
Divider output to generate the CLKOS signal. The phase/duty cycle setting can be pre-programmed or dynamically
adjusted.
The clock outputs from the GPLL; CLKOP, CLKOK, CLKOK2 and CLKOS, are fed to the clock distribution network.
For further information on the GPLL please see TN1126,
LatticeXP2 sysCLOCK PLL Design and Usage
Guide.
2-6