SC16C850LIET-S NXP Semiconductors, SC16C850LIET-S Datasheet - Page 14

• Manufacturer Part Number: SC16C850LIET-S
• Manufacturer: NXP Semiconductors

Specifications of SC16C850LIET-S

• Transmitter And Receiver Fifo Counter: Yes
• Data Rate: 5Mbps
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SC16C850L
Product data sheet
6.9 Programmable baud rate generator
each time the Receive Holding Register (RHR) is read. The actual time-out value is
4 character time, including data information length, start bit, parity bit, and the size of stop
bit, that is, 1, 1.5, or 2 bit times.
The SC16C850L UART contains a programmable rational baud rate generator that takes
any clock input and divides it by a divisor in the range between 1 and (2
SC16C850L offers the capability of dividing the input frequency by rational divisor. The
fractional part of the divisor is controlled by the CLKPRES register in the ‘first extra feature
register set’.
where:
Prescaler = 1 when MCR[7] is set to 0.
Prescaler = 4 when MCR[7] is set to 1.
A single baud rate generator is provided for the transmitter and receiver. The
programmable Baud Rate Generator is capable of operating with a frequency of up to
80 MHz. To obtain maximum data rate, it is necessary to use full rail swing on the clock
input. The SC16C850L can be configured for internal or external clock operation. For
internal clock operation, an industry standard crystal is connected externally between the
XTAL1 and XTAL2 pins (see
to the XTAL1 pin (see
custom rates (see
The generator divides the input 16 clock by any divisor from 1 to (2
SC16C850L divides the basic external clock by 16. The baud rate is configured via the
CLKPRES, DLL and DLM internal register functions. Customized baud rates can be
achieved by selecting the proper divisor values for the MSB and LSB sections of the baud
rate generator.
baud rate
Fig 6. Prescalers and baud rate generator block diagram
N is the integer part of the divisor in DLL and DLM registers;
M is the fractional part of the divisor in CLKPRES register;
f
XTAL1
XTAL1
XTAL2
is the clock frequency at XTAL1 pin.
=
OSCILLATOR
------------------------------------------------------------------ -
MCR 7  
All information provided in this document is subject to legal disclaimers.
Table
1.8 V single UART with 128-byte FIFOs and IrDA encoder/decoder

Figure
Rev. 5 — 1 February 2011
f
XTAL1
7).
16

DIVIDE-BY-1
DIVIDE-BY-4
Figure
8) to clock the internal baud rate generator for standard or


N
+
----- -
16
M
7). Alternatively, an external clock can be connected


MCR[7] = 0
MCR[7] = 1
GENERATOR
BAUD RATE
(DLL, DLM)
CLKPRES
[3:0]
SC16C850L
16
 1). The
© NXP B.V. 2011. All rights reserved.
16
 1). The
transmitter and
receiver clock
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