SC16C850LIET-S NXP Semiconductors, SC16C850LIET-S Datasheet - Page 9

• Manufacturer Part Number: SC16C850LIET-S
• Manufacturer: NXP Semiconductors

Specifications of SC16C850LIET-S

• Transmitter And Receiver Fifo Counter: Yes
• Data Rate: 5Mbps
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
6. Functional description
SC16C850L
Product data sheet
6.1 UART selection
The SC16C850L provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessary for converting the serial data stream into
parallel data that is required with digital data systems. Synchronization for the serial data
stream is accomplished by adding start and stop bits to the transmit data to form a data
character (character orientated protocol). Data integrity is ensured by attaching a parity bit
to the data character. The parity bit is checked by the receiver for any transmission bit
errors. The electronic circuitry to provide all these functions is fairly complex, especially
when manufactured on a single integrated silicon chip. The SC16C850L represents such
an integration with greatly enhanced features. The SC16C850L is fabricated with an
advanced CMOS process.
The SC16C850L is an upward solution to the SC16C650B that provides a single UART
capability with 128 bytes of transmit and receive FIFO memory, instead of 32 bytes for the
16C650B and 16 bytes in the 16C550B. The SC16C850L is designed to work with high
speed modems and shared network environments that require fast data processing time.
Increased performance is realized in the SC16C850L by the transmit and receive FIFOs.
This allows the external processor to handle more networking tasks within a given time. In
addition, the four selectable receive and transmit FIFO trigger interrupt levels are provided
in 16C650 mode, or 128 programmable levels are provided in the extended mode for
maximum data throughput performance especially when operating in a multi-channel
environment (see
greatly reduces the bandwidth requirement of the external controlling CPU and increases
performance. A low power pin (LOWPWR) is provided to further reduce power
consumption by isolating the host bus interface.
The SC16C850L is capable of operation up to 5 Mbit/s with an external 80 MHz clock.
With a crystal, the SC16C850L is capable of operation up to 1.5 Mbit/s.
The rich feature set of the SC16C850L is available through internal registers. These
features are: selectable and programmable receive and transmit FIFO trigger levels,
selectable TX and RX baud rates, and modem interface controls, and are all standard
features. Following a power-on reset, an external reset, or a software reset, the
SC16C850L is software compatible with the previous generation, SC16C550B, and
SC16C650B.
The UART provides the user with the capability to bidirectionally transfer information
between an external CPU, the SC16C850L package, and an external serial device. A
logic 0 (LOW) on chip select pin CS allows the user to configure, send data, and/or
receive data via the UART. Refer to
Table 3.
H = HIGH; L = LOW.
Chip Select
CS = L
CS = H
Serial port selection (Intel interface)
All information provided in this document is subject to legal disclaimers.
Section 6.2 “Extended mode (128-byte
1.8 V single UART with 128-byte FIFOs and IrDA encoder/decoder
Function
none
UART select
Rev. 5 — 1 February 2011
Table 3
and
Table
4.
FIFO)”). The FIFO memory
SC16C850L
© NXP B.V. 2011. All rights reserved.
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