87016AYIT IDT, Integrated Device Technology Inc, 87016AYIT Datasheet

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87016AYIT

Manufacturer Part Number
87016AYIT
Description
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Dividerr
Datasheet

Specifications of 87016AYIT

Number Of Clock Inputs
2
Output Frequency
250MHz
Output Logic Level
LVCMOS/LVTTL
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.465V
Package Type
TQFP
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Lead Free Status / RoHS Status
Not Compliant
Block Diagram
LOW SKEW, 1-TO-16 LVCMOS/LVTTL
CLOCK GENERATOR
Description
÷2 frequency operation. Each bank also has its own power supply
pins so that the banks can operate at the following different
voltage levels: 3.3V, 2.5V, and 1.8V. The low impedance
LVCMOS/LVTTL outputs are designed to drive 50Ω series or
parallel terminated transmission lines.
The divide select inputs, DIV_SELA:DIV_SELD, control the output
frequency of each bank. The output banks can be independently
selected for ÷1 or ÷2 operation. The bank enable inputs,
CLK_ENA:CLK_END, support enabling and disabling each bank
of outputs individually. The CLK_ENA:CLK_END circuitry has a
synchronizer to prevent runt pulses when enabling or disabling the
clock outputs. The master reset input, MR/OE, resets the ÷1/÷2
flip flops and also controls the active and high impedance states of
all outputs. This pin has an internal pull-up resistor and is normally
used only for test purposes or in systems which use low power
modes.
The ICS87016I is characterized to operate with the core at 3.3V or
2.5V and the banks at 3.3V, 2.5V, or 1.8V. Guaranteed bank,
output, and part-to-part skew characteristics make the 87016I
ideal for those clock applications demanding well-defined
performance and repeatability.
IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR
DIV_SELD
DIV_SELC
HiPerClockS™
DIV_SELA
DIV_SELB
CLK_ENC
CLK_END
CLK_ENA
CLK_ENB
CLK_SEL
ICS
MR/OE
CLK0
CLK1
CLK1
The ICS87016I is a low skew, 1:16 LVCMOS/LVTTL
Clock Generator and is a member of the
HiPerClockS family of High Performance Clock
Solutions. The device has 4 banks of 4 outputs and
each bank can be independently selected for ÷1 or
0
1
÷1
÷2
1
0
1
0
1
0
1
0
D
LE
D
LE
D
LE
D
LE
4
4
4
4
QA0:QA3
QB0:QB3
QC0:QC3
QD0:QD3
1
Features
Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs)
Selectable differential CLK1/CLK1 or LVCMOS/LVTTL clock
input
CLK1, CLK1 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
CLK0 supports the following input types: LVCMOS, LVTTL
Maximum output frequency: 250MHz
Independent bank control for ÷1 or ÷2 operation
Independent output bank voltage settings for 3.3V, 2.5V, or 1.8V
operation
Asynchronous clock enable/disable
Output skew: 170ps (maximum)
Bank skew: 50ps (maximum
Part-to-Part Skew: 800ps (maximum)
Supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
DIV_SELC
DIV_SELD
DIV_SELA
DIV_SELB
CLK_ENA
CLK_ENB
CLK_END
CLK_ENC
MR/OE
CLK0
GND
V
7mm x 7mm x 1.4mm package body
DD
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
48-Lead LQFP
ICS87016AYI REV. C MAY 25, 2007
Y Package
ICS87016I
Top View
ICS87016I
36
35
34
33
32
31
30
29
28
27
26
25
GND
QB0
V
QB1
GND
QB2
V
QB3
GND
QC0
V
QC1
DDOB
DDOB
DDOC

Related parts for 87016AYIT

87016AYIT Summary of contents

Page 1

LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR Description The ICS87016I is a low skew, 1:16 LVCMOS/LVTTL ICS Clock Generator and is a member of the HiPerClockS family of High Performance Clock HiPerClockS™ Solutions. The device has 4 banks of 4 outputs ...

Page 2

ICS87016I LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR Table 1. Pin Descriptions Number Name Power DD 2 CLK0 Input 3 DIV_SELA Input 4 DIV_SELB Input 5 DIV_SELC Input 6 DIV_SELD Input 7 CLK_ENA Input 8 CLK_ENB Input 9 ...

Page 3

ICS87016I LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR Table 2. Pin Characteristics Symbol Parameter C Input Capacitance IN Input Pullup Resistor R PULLUP R Input Pulldown Resistor PULLDOWN Power Dissipation Capacitance C PD (per output); NOTE 1 R Output Impedance OUT ...

Page 4

ICS87016I LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or ...

Page 5

ICS87016I LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR Table 4C. LVCMOS/LVTTL DC Characteristics, T Symbol Parameter V Input High Voltage IH V Input Low Voltage IL CLK0, CLK_SEL Input I IH High Current CLK_EN[A:D], DIV_SEL[A:D], MR/OE CLK0, CLK_SEL Input I IL ...

Page 6

ICS87016I LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR AC Electrical Characteristics Table 5A. AC Characteristics, V Parameter Symbol f Output Frequency MAX CLK0; NOTE 1A Propagation Delay Low to High CLK1/CLK1; NOTE 1B tsk(b) Bank Skew; NOTE 2, 6 ...

Page 7

ICS87016I LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR Table 5C. AC Characteristics, V Parameter Symbol f Output Frequency MAX CLK0; NOTE 1A Propagation Delay Low to High CLK1/CLK1; NOTE 1B tsk(b) Bank Skew; NOTE 2, 6 tsk(o) Output Skew; ...

Page 8

ICS87016I LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR Table 5E. AC Characteristics, V Parameter Symbol f Output Frequency MAX CLK0; NOTE 1A Propagation tp Delay, CLK1/CLK1; LH Low to High NOTE 1B tsk(b) Bank Skew; NOTE 2, 6 tsk(o) Output Skew; ...

Page 9

ICS87016I LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR Parameter Measurement Information 1.65V±5% V DD, V DDO LVCMOS GND -1.65V±5% - 3.3V Core/3.3V LVCMOS Output Load AC Test Circuit 2.05V±5% 1.25V± DDO GND LVCMOS -1.25V±5% 3.3V Core/2.5V LVCMOS Output ...

Page 10

ICS87016I LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR Parameter Measurement Information, continued V DDOX DDOX Qy 2 tsk(o) Output Skew CLK1 CLK1 CLK0 V DDO QA0:QA3, 2 QB0:QB3 QC0:QC3, QD0:QD3 Propagation Delay 80% ...

Page 11

ICS87016I LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR Application Information Wiring the Differential Input to Accept Single Ended Levels Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V generated ...

Page 12

ICS87016I LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR Differential Clock Input Interface The CLK /CLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both signals must meet the V V input requirements. Figures show interface CMR ...

Page 13

ICS87016I LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR Reliability Information θ Table 6. vs. Air Flow Table for a 48 Lead LQFP JA Linear Feet per Minute Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most ...

Page 14

ICS87016I LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR Package Outline and Package Dimension Package Outline - Y Suffix for 48 Lead LQFP Table 7. Package Dimensions for 48 Lead LQFP JEDEC Variation: ABC - HD All Dimensions in Millimeters Symbol Minimum ...

Page 15

... LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR Ordering Information Table 8. Ordering Information Part/Order Number Marking ICS87016AYI ICS87016AYI ICS87016AYIT ICS87016AYI ICS87016AYILF TBD ICS87016AYILFT TBD NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. ...

Page 16

ICS87016I LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR Revision History Sheet Rev Table Page T4B 4 T4C 5 T4D 5 B T5B 6 T5E T5B 6 IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR Description ...

Page 17

ICS87016I DIFFERENTIAL-TO-LVPECL FANOUT BUFFER W/DIVIDER AND GLITCHLESS SWITCH Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United ...

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