PIC16F1526-I/PT Microchip Technology, PIC16F1526-I/PT Datasheet - Page 86
![MCU 14KB FLASH 768B RAM 64-TQFP](/photos/16/3/160367/tqfp-64_sml.jpg)
PIC16F1526-I/PT
Manufacturer Part Number
PIC16F1526-I/PT
Description
MCU 14KB FLASH 768B RAM 64-TQFP
Manufacturer
Microchip Technology
Datasheet
1.PIC16F1526-IPT.pdf
(354 pages)
Specifications of PIC16F1526-I/PT
Processor Series
PIC16F
Core
PIC
Program Memory Type
Flash
Program Memory Size
14 KB
Data Ram Size
768 B
Interface Type
MI2C, SPI, EUSART
Number Of Timers
9
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
TQFP-64
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F1526-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC16F1526-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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PIC16(L)F1526/27
7.6.7
The PIR2 register contains the interrupt flag bits, as
shown in
REGISTER 7-7:
DS41458A-page 86
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W-0/0
OSFIF
Register
PIR2 REGISTER
OSFIF: Oscillator Fail Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
TMR5GIF: Timer5 Gate Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
TMR3GIF: Timer3 Gate Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Unimplemented: Read as ‘0’
BCL1IF: MSSP1 Bus Collision Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
TMR10IF: Timer10 to PR10 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
TMR8IF: Timer8 to PR8 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
CCP2IF: CCP2 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
TMR5GIF
7-7.
R/W-0/0
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
TMR3GIF
R/W-0/0
U-0
Preliminary
—
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
R/W-0/0
BCL1IF
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
TMR10IF
R/W-0/0
software
2011 Microchip Technology Inc.
R/W-0/0
TMR8IF
should
ensure
R/W-0/0
CCP2IF
bit 0
the
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