LPC1850FET256,551 NXP Semiconductors, LPC1850FET256,551 Datasheet
LPC1850FET256,551
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LPC1850/30/20/10 32-bit ARM Cortex-M3 MCU 200 kB SRAM; Ethernet, two High-speed USB, LCD, and external memory controller Rev. 1.2 — 17 February 2011 1. General description The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embedded applications. The ARM ...
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... NXP Semiconductors Two PLLs allow CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. Second PLL can be used for USB. Clock output. Serial interfaces: Quad SPI Flash Interface (SPIFI) with four lanes and data rates per second total. ...
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... NXP Semiconductors Analog peripherals: One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s. Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s. Security: Hardware-based AES security engine programmable through an on-chip API. ...
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... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Name LPC1850FET256 LBGA256 LPC1850 LQFP208 LPC1850 BGA180 LPC1830FET256 LBGA256 LPC1830 LQFP208 LPC1830 BGA180 LPC1820 LQFP144 LPC1820FET100 BGA100 LPC1810 LQFP144 LPC1810FET100 BGA100 4.1 Ordering options Table 2. Ordering options Type number SRAM LPC1850 ...
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... NXP Semiconductors 5. Block diagram SWD/TRACE PORT/JTAG TEST/DEBUG INTERFACE ARM CORTEX-M3 BRIDGE 0 BRIDGE 1 MOTOR WWDT CONTROL USART0 PWM UART1 SSP0 TIMER0 TIMER1 SCU = connected to GPDMA (1) Not available on all parts (see Fig 1. LPC1850/30/20/10 block diagram LPC1850_30_20_10 Objective data sheet HIGH-SPEED PHY HIGH- (1) ETHERNET ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. 6.2 Pin description On the LPC1850/30/20/10, digital pins are grouped into 16 ports, named and PA to PF, with pins used per port. Each digital pin may support up to four different digital functions, including General Purpose I/O (GPIO), selectable through the SCU registers ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Reset state [1] [2] P1_0 [ P1_1 [2] P1_2 [2] P1_3 [2] P1_4 [2] P1_5 [2] P1_6 [2] P1_7 [2] P1_8 LPC1850_30_20_10 Objective data sheet Type Description I/O GPIO0[4] — General purpose digital input/output pin. I CTIN_3 — SCT input 3. Capture input 1 of timer 1. ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Reset state [1] [2] P1_9 [ P1_10 [ P1_11 [ P1_12 [2] R10 I; PU P1_13 [2] R11 I; PU P1_14 [2] P1_15 T12 I; PU [2] P1_16 [2] P1_17 LPC1850_30_20_10 Objective data sheet Type Description I/O GPIO1[2] — General purpose digital input/output pin. O U1_RTS — Request to Send output for UART1. ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Reset state [1] [2] P1_18 N12 I; PU [2] M11 I; PU P1_19 [2] P1_20 M10 I; PU [2] P2_0 T16 I; PU [2] P2_1 N15 I; PU [2] P2_2 M15 I; PU [2] P2_3 J12 I; PU [2] P2_4 K11 I; PU LPC1850_30_20_10 Objective data sheet Type Description I/O GPIO0[13] — ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Reset state [1] [3] P2_5 K14 I; PU [2] P2_6 K16 I; PU [2] P2_7 H14 I; PU [2] P2_8 J16 I; PU [2] P2_9 H16 I; PU [2] P2_10 G16 I; PU [2] P2_11 F16 I; PU [2] P2_12 E15 I; PU [2] P2_13 C16 I; PU LPC1850_30_20_10 Objective data sheet ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Reset state [1] [2] P3_0 F13 I; PU [2] P3_1 G11 I; PU [2] P3_2 F11 I; PU [2] P3_3 B14 I; PU [2] P3_4 A15 I; PU [2] P3_5 C12 I; PU [2] P3_6 B13 I; PU [2] P3_7 C11 I; PU LPC1850_30_20_10 Objective data sheet Type Description I/O I2S_RX_SCK — ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Reset state [1] [2] P3_8 C10 P4_0 [ P4_1 [ P4_2 [ P4_3 [ P4_4 [2] P4_5 [2] P4_6 [2] P4_7 H4 O;PU LPC1850_30_20_10 Objective data sheet Type Description - n.c. - n.c. I/O SSP0_MOSI — Master Out Slave in for SSP0. I/O SPIFI_CS — SPIFI serial flash chip select. ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Reset state [1] [2] P4_8 [ P4_9 [ P4_10 [ P5_0 [ P5_1 [ P5_2 [2] P5_3 [2] P5_4 [2] P5_5 P10 I; PU LPC1850_30_20_10 Objective data sheet Type Description - n.c. I CTIN_5 — SCT input 5. Capture input 2 of timer 2. O LCDVD9 — LCD data. ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Reset state [1] [2] P5_6 T13 I; PU [2] R12 I; PU P5_7 P6_0 M12 I; PU [2] P6_1 R15 I; PU [2] P6_2 L13 I; PU [2] P6_3 P15 I; PU [2] P6_4 R16 I; PU [2] P6_5 P16 I; PU LPC1850_30_20_10 Objective data sheet Type Description I/O GPIO2[15] — ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Reset state [1] [2] P6_6 L14 I; PU [2] P6_7 J13 I; PU [2] P6_8 H13 I; PU [2] P6_9 J15 I; PU [2] P6_10 H15 I; PU [2] P6_11 H12 I; PU [2] P6_12 G15 I; PU [2] P7_0 B16 I; PU [2] P7_1 C14 I; PU LPC1850_30_20_10 Objective data sheet ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Reset state [1] [2] P7_2 A16 I; PU [2] P7_3 C13 I; PU [2] P7_4 [2] P7_5 [2] P7_6 [2] P7_7 [2] P8_0 [2] P8_1 [2] P8_2 LPC1850_30_20_10 Objective data sheet Type Description I/O GPIO3[10] — General purpose digital input/output pin. I CTIN_4 — SCT input 4. Capture input 2 of timer 1. ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Reset state [1] [2] P8_3 [ P8_4 [ P8_5 [ P8_6 [2] P8_7 [2] P8_8 [2] P9_0 [2] P9_1 [2] P9_2 LPC1850_30_20_10 Objective data sheet Type Description I/O GPIO4[3] — General purpose digital input/output pin. I/O USB1_ULPI_D2 — ULPI link bidirectional data line 2. ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Reset state [1] [2] P9_3 [2] N10 I; PU P9_4 [ P9_5 [2] L11 I; PU P9_6 [2] PA_0 L12 I; PU [2] PA_1 J14 I; PU [2] PA_2 K15 I; PU [2] PA_3 H11 I; PU [2] PA_4 G13 I; PU LPC1850_30_20_10 Objective data sheet Type Description I/O GPIO4[15] — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Reset state [1] [2] PB_0 B15 I; PU [2] A14 I; PU PB_1 [2] PB_2 B12 I; PU [2] PB_3 A13 I; PU [2] PB_4 B11 I; PU [2] PB_5 A12 I; PU [2] PB_6 [2] PC_0 [2] PC_1 LPC1850_30_20_10 Objective data sheet Type Description - n.c. O CTOUT_10 — SCT output 10. Match output 2 of timer 2. ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Reset state [1] [2] PC_2 [ PC_3 [2] PC_4 [2] PC_5 [2] PC_6 [2] PC_7 [2] PC_8 [2] PC_9 [2] PC_10 LPC1850_30_20_10 Objective data sheet Type Description I/O USB1_ULPI_D6 — ULPI link bidirectional data line 6. O SDIO_RST — SD/MMC reset signal for MMC4.4 card. ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Reset state [1] [2] PC_11 [2] PC_12 [2] PC_13 [2] PC_14 [2] PD_0 [2] PD_1 [2] PD_2 [2] PD_3 [2] PD_4 LPC1850_30_20_10 Objective data sheet Type Description I/O SDIO_D4 — SD/MMC data bus line 4. I USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULP data line direction ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Reset state [1] [2] PD_5 [ PD_6 [ PD_7 [ PD_8 [2] T11 I; PU PD_9 [2] P11 I; PU PD_10 [2] PD_11 [2] PD_12 N11 I; PU [2] PD_13 T14 I; PU LPC1850_30_20_10 Objective data sheet Type Description - n.c. O CTOUT_9 — SCT output 9. Match output 1 of timer 2. ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Reset state [1] [2] PD_14 R13 I; PU [2] PD_15 T15 I; PU [2] R14 I; PU PD_16 [2] P14 I; PU PE_0 [2] N14 I; PU PE_1 [2] M14 I; PU PE_2 [2] PE_3 K12 I; PU [2] PE_4 K13 I; PU [2] PE_5 N16 I; PU LPC1850_30_20_10 Objective data sheet ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Reset state [1] [2] PE_6 M16 I; PU [2] F15 I; PU PE_7 [2] F14 I; PU PE_8 [2] E16 I; PU PE_9 [2] E14 I; PU PE_10 [2] PE_11 D16 I; PU [2] PE_12 D15 I; PU [2] PE_13 G14 I; PU [2] PE_14 C15 I; PU LPC1850_30_20_10 Objective data sheet ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Reset state [1] [2] PE_15 E13 I; PU [2] PF_0 D12 I;IA [2] PF_1 E11 I; PU [2] PF_2 D11 I; PU [2] PF_3 E10 I; PU [2] PF_4 D10 I;IA [2] PF_5 [2] PF_6 [2] PF_7 LPC1850_30_20_10 Objective data sheet Type Description - n.c. O CTOUT_0 — SCT output 0. Match output 0 of timer 0. ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Reset state [1] [2] PF_8 [ PF_9 [ PF_10 [ PF_11 Clock pins [4] CLK0 [2] CLK1 T10 O; PU [2] CLK2 D14 O; PU [2] CLK3 P12 O; PU Debug pins [2] DBGEN [2] TCK/SWDCLK [2] TRST [2] TMS/SWDIO [2] TDO/SWO LPC1850_30_20_10 Objective data sheet Type Description - n.c. I/O U0_UCLK — ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Reset state [1] [2] TDI C-bus pins [8] I2C0_SCL L15 I; F [8] I2C0_SDA L16 I; F USB0 pins [5] USB0_DP F2 - [5] USB0_DM G2 - [5] USB0_VBUS F1 - [6] USB0_ID H2 - [6] USB0_RREF H1 - USB1 pins [7] USB1_DP F12 - [7] USB1_DM G12 - Reset and wake-up pins [9] RESET D9 I ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Reset state [1] Crystal oscillator pins [6] XTAL1 D1 - [6] XTAL2 E1 - Power and ground pins USB0_VDDA3V3_ F3 - DRIVER USB0_VDDA3V3 G3 - USB0_VSSA_TERM H3 - USB0_VSSA_REF G1 - VDDA B4 - VBAT B10 - VDDREG F10; - F9; L8; L7; VPP E8 - VDDIO F7; - J7; N7; L10; E12; N13; L9; H10; G10; D7; J6; F8; K7 VSSA ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Reset state [1] VSSIO G6; - J8; J9; K9; K10; P7; M13; P13; D13; G8; H8; G7; C4; H9 Pins not connected - input output inactive pull-up enabled pull-down enabled floating. [2] Digital I/O pin. Not 5 V tolerant. [3] Digital I/O pin tolerant. [4] Digital high-speed I/O pin. ...
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... NXP Semiconductors 7. Functional description 7.1 Architectural overview The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus. The I-code and D-code core buses allow for concurrent code and data accesses from different slave ports. ...
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... NXP Semiconductors 7.3 AHB multilayer matrix TEST/DEBUG INTERFACE ARM CORTEX-M3 System I-code D-code bus bus bus AHB MULTILAYER MATRIX = master-slave connection (1) Not available on all parts (see Fig 3. AHB multilayer matrix master and slave connections 7.4 Nested Vectored Interrupt Controller (NVIC) The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts ...
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... NXP Semiconductors 7.4.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. 7.5 Event router The event router combines various internal signals, interrupts, and the external interrupt ...
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... NXP Semiconductors • Secure booting from an encrypted image. In development mode booting from a plain text image is possible. Development mode is terminated by programming the AES key. • API for AES programming. Several boot modes are available depending on the values of the OTP bits BOOT_SRC. If the OTP memory is not programmed or the BOOT_SRC bits are all zero, the boot mode is determined by the states of the boot pins P2_8, P1_2, and P1_1 ...
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... NXP Semiconductors Table 5. Boot mode USB0 USB1 SPI (SSP) [1] The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI. LPC1850_30_20_10 Objective data sheet Boot mode when OPT BOOT_SRC bits are zero P2_7 P2_8 P1_2 HIGH HIGH LOW ...
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... NXP Semiconductors 7.9 Memory mapping 0x2000 0000 16 MB static external memory CS3 0x1F00 0000 16 MB static external memory CS2 0x1E00 0000 16 MB static external memory CS1 0x1D00 0000 16 MB static external memory CS0 0x1C00 0000 reserved 0x1040 8000 32 kB ROM 0x1040 0000 ...
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LPC1850/30/20/10 0x400F 0000 reserved 0x400E 5000 ADC1 0x400E 4000 ADC0 APB3 0x400E 3000 peripherals C_CAN 0x400E 2000 DAC 0x400E 1000 I2C1 0x400E 0000 0x400D 0000 reserved 0x400C 7000 QEI 0x400C 6000 SSP1 0x400C 5000 APB2 timer3 0x400C 4000 peripherals timer2 ...
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... NXP Semiconductors 7.10 Security features 7.10.1 AES security engine The hardware AES security engine can encrypt algorithm in conjunction with a 128-bit key. 7.10.1.1 Features • Decryption of external flash data connected to the quad SPI Flash Interface (SPIFI). • Secure storage of keys. • Support for CMAC hash calculation to authenticate encrypted data. ...
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... NXP Semiconductors 7.12 AHB peripherals 7.12.1 State Configurable Timer (SCT) subsystem The SCT allows a wide variety of timing, counting, output modulation, and input capture operations. The inputs and outputs of the SCT are shared with the capture and match inputs/outputs of the 32-bit general purpose counter/timers. ...
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... NXP Semiconductors example, a bidirectional port requires one stream for transmit and one for receives. The source and destination areas can each be either a memory region or a peripheral for master 1, but only memory for master 0. 7.12.2.1 Features • Eight DMA channels. Each channel can support an unidirectional transfer. ...
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... NXP Semiconductors commands and command formats. SPIFI provides sufficient flexibility to be compatible with common flash devices and includes extensions to help insure compatibility with future devices. 7.12.3.1 Features • Interfaces to serial flash memory in the main memory map. • Supports classic and 4-bit bidirectional serial protocols. ...
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... NXP Semiconductors • Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row address synchronous memory parts. That is typical 512 MB, 256 MB, and 128 MB parts, with data bits per device. • Separate reset domains allow the for auto-refresh through a chip reset if desired. ...
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... NXP Semiconductors 7.12.8 LCD controller The LCD controller provides all of the necessary control signals to interface directly to a variety of color and monochrome LCD panels. Both STN (single and dual panel) and TFT panels can be operated. The display resolution is selectable and can 1024 768 pixels ...
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... NXP Semiconductors • IP checksum • DMA support • Power management remote wake-up frame and magic packet detection • Supports both full-duplex and half-duplex operation – Supports CSMA/CD Protocol for half-duplex operation. – Supports IEEE 802.3x flow control for full-duplex operation. – Optional forwarding of received pause control frames to the user application in full-duplex operation. – ...
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... NXP Semiconductors 7.13.2.1 Features • Maximum UART data bit rate of <tbd> MBit/s. • Receive and Transmit FIFOs. • Register locations conform to 16C550 industry standard. • Receiver FIFO trigger points and 14 B. • Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. • ...
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... NXP Semiconductors 7.13.4.1 Features • standard I supports Fast mode plus with bit rates Mbit/s. • uses standard I/O pins with bit rates 400 kbit/s (Fast I • Easy to configure as master, slave, or master/slave. • Programmable clocks allow versatile rate control. • Bidirectional data transfer between masters and slaves. ...
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... NXP Semiconductors 7.13.6 C_CAN Controller Area Network (CAN) is the definition of a high performance communication protocol for serial data communication. The C_CAN controller is designed to provide a full implementation of the CAN protocol according to the CAN Specification Version 2.0B. The C_CAN controller allows to build powerful local networks with low-cost multiplex wiring by supporting distributed real-time control with a very high level of security ...
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... NXP Semiconductors • two match registers can be used to generate timed DMA requests. 7.14.2 Motor control PWM The motor control PWM is a specialized PWM supporting 3-phase motors and other combinations. Feedback inputs are provided to automatically sense rotor position and use that information to ramp speed up or down. An abort input is also provided that causes the PWM to immediately release all motor drive outputs ...
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... NXP Semiconductors • 32-bit compare mask. An interrupt is generated when the counter value equals the compare value, after masking. This allows for combinations not possible with a simple compare. 7.14.5 Windowed WatchDog Timer (WWDT) The purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window ...
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... NXP Semiconductors • Integral Non-Linearity • Differential Non-Linearity • Monotonic by design (resistor string architecture) • Controllable conversion speed • Low power consumption 7.16 Peripherals in the RTC power domain 7.16.1 RTC The Real Time Clock (RTC set of counters for measuring time when system power is on, and optionally when it is off ...
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... NXP Semiconductors In addition, the CREG block contains the part identification and part configuration information. 7.17.2 System Control Unit (SCU) The system control unit determines the function and electrical mode of the digital pins. By default function 0 is selected for all pins with pull-up enabled. ...
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... NXP Semiconductors 7.17.8 Power control The LPC1850/30/20/10 support four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down. The LPC1850/30/20/10 can wake up from Deep-sleep, Power-down, and Deep power-down modes via the WAKEUP[3:0] pins and interrupts generated by battery powered blocks in the RTC power domain. ...
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... NXP Semiconductors 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V regulator supply voltage (3.3 V) DD(REG)(3V3) V input/output supply voltage DD(IO) V analog supply voltage (3.3 V) DDA(3V3) V battery supply voltage BAT V polyfuse programming voltage prog(pf) ...
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... NXP Semiconductors 9. Thermal characteristics The average chip junction temperature, T equation amb • T amb • R th(j-a) • The internal power dissipation is the product of I the I/O pins is often small and many times can be negligible. However it can be significant in some applications. Table 7. Thermal characteristics ...
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... NXP Semiconductors 10. Static characteristics Table 8. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter Supply pins V input/output supply DD(IO) voltage V regulator supply voltage DD(REG)(3V3) (3 analog supply voltage DDA(3V3) (3 battery supply voltage BAT I regulator supply current DD(REG)(3V3) (3 ...
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... NXP Semiconductors Table 8. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter Digital pins I LOW-level input current HIGH-level input IH current I OFF-state output OZ current V input voltage I V output voltage O V HIGH-level input IH voltage V LOW-level input voltage IL V hysteresis voltage ...
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... NXP Semiconductors Table 8. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter Oscillator pins V input voltage on pin i(XTAL1) XTAL1 V output voltage on pin o(XTAL2) XTAL2 USB pins V common-mode input IC voltage V differential input voltage i(dif) Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. ...
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... NXP Semiconductors 10.1 Electrical pin characteristics <tbd> Conditions: V DD(REG)(3V3) port pins. Fig 6. Typical HIGH-level output voltage V HIGH-level output source current ( <tbd> Conditions: V DD(REG)(3V3) port pins. Fig 8. Typical pull-up current LPC1850_30_20_10 Objective data sheet 001aab173 ( 3.3 V; standard DD(IO) versus Fig 7 ...
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... NXP Semiconductors 10.2 Power consumption <tbd> C; V Conditions: T amb Fig 10. Typical supply current versus regulator supply voltage V DD(REEG)(3V3 ( <tbd> C; <tbd>. Conditions: T amb Fig 12. Typical supply current versus temperature in Sleep mode LPC1850_30_20_10 Objective data sheet 001aab173 (X) = 3.3 V; <tbd> DD(REEG)(3V3) Fig 11 ...
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... NXP Semiconductors <tbd> C; <tbd>. Conditions: T amb Fig 14. Typical supply current versus temperature in Power-down mode LPC1850_30_20_10 Objective data sheet 001aab173 (X) Fig 15. Typical supply current versus temperature in All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 17 February 2011 LPC1850/30/20/10 ...
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... NXP Semiconductors Table amb Peripheral IRC ADC DAC I2C0 I2C1 I2S SSP0 SSP1 USART0 UART1 USART2 USART3 USB0 USB1 Ethernet <tbd> Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply [1] voltages. LPC1850_30_20_10 Objective data sheet Power consumption for individual peripherals ...
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... NXP Semiconductors 11. Dynamic characteristics 11.1 External clock Table 10. amb Symbol Parameter f osc T cy(clk) t CHCX t CLCX t CLCH t CHCL [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply [2] voltages ...
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... NXP Semiconductors 11.2 IRC and RTC oscillators Table 11. amb Symbol f osc(RC) f i(RTC) [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply [2] voltages. Fig 17. Internal RC oscillator frequency versus temperature 2 11 ...
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... NXP Semiconductors Table 12. Dynamic characteristic: I [ +85 C. amb Symbol Parameter t LOW period of the SCL clock LOW t HIGH period of the SCL clock HIGH t data hold time HD;DAT t data set-up time SU;DAT [1] Parameters are valid over operating temperature range unless otherwise specified. ...
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... NXP Semiconductors SDA SCL SCL 2 Fig 18. I C-bus pins clock timing LPC1850_30_20_10 Objective data sheet t SU;DAT HD;DAT LOW All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 17 February 2011 LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller t VD;DAT t HIGH © NXP B.V. 2011. All rights reserved. ...
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... NXP Semiconductors 11.4 SSP interface Table 13. Dynamic characteristics: SSP pins in SPI mode Symbol Parameter T PCLK cycle time cy(PCLK) T clock cycle time cy(clk) SSP master t data set-up time DS t data hold time DH t data output valid time v(Q) t data output hold time ...
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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 19. SSP master timing in SPI mode LPC1850_30_20_10 Objective data sheet T cy(clk) t v(Q) DATA VALID MOSI MISO DATA VALID t v(Q) DATA VALID MOSI t DATA VALID MISO All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 17 February 2011 ...
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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 20. SSP slave timing in SPI mode LPC1850_30_20_10 Objective data sheet T cy(clk) MOSI DATA VALID t v(Q) MISO DATA VALID t MOSI DATA VALID t v(Q) MISO DATA VALID All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 17 February 2011 ...
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... NXP Semiconductors 11.5 USB interface Table 14. Dynamic characteristics: USB pins (full-speed) pF 1 Symbol Parameter t rise time r t fall time f t differential rise and fall time FRFM matching V output signal crossover voltage CRS t source SE0 interval of EOP FEOPT t source jitter for differential transition ...
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... NXP Semiconductors 11.6 Dynamic external memory interface Table 15. Dynamic characteristics: Dynamic external memory interface pF amb Symbol Parameter Common t chip select valid delay time d(SV) t chip select hold time h(S) t row address strobe valid delay time d(RASV) t row address strobe hold time ...
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Static external memory interface Table 16. Dynamic characteristics: Static external memory interface pF and V L amb DD(REG)(3V3) Symbol Parameter Conditions [1] Common to read ...
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Table 16. Dynamic characteristics: Static external memory interface pF and V L amb DD(REG)(3V3) Symbol Parameter Conditions t WE HIGH to data invalid WEHDNV time t ...
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... NXP Semiconductors CS addr data t CSLOEL OE BLS Fig 22. Static external memory controller read access CS BLS/WE addr data OE Fig 23. Static external memory controller write access LPC1850_30_20_10 Objective data sheet t CSLAV OELAV t OELOEH t BLSLAV t CSLAV t WELWEH t CSLWEL t BLSLBLSH t t CSLBLSL WELDV t CSLDV All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 12. ADC/DAC electrical characteristics Table 17. ADC characteristics V over specified ranges; T DDA(3V3) Symbol Parameter V analog input voltage IA C analog input capacitance ia E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error G E absolute error T R voltage source interface ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 24. 10-bit ADC characteristics LPC1850_30_20_10 ...
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... NXP Semiconductors Table 18. DAC electrical characteristics V over specified ranges; T DDA(3V3) Symbol Parameter E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error G C load capacitance L R load resistance L LPC1850_30_20_10 Objective data sheet +85 C; unless otherwise specified ...
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... NXP Semiconductors 13. Application information 13.1 LCD panel signal usage Table 19. LCD panel connections for STN single panel mode External pin 4-bit mono STN single panel LPC18xx pin used LCDVD[23:8] - LCDVD7 - LCDVD6 - LCDVD5 - LCDVD4 - LCDVD3 P4_2 LCDVD2 P4_3 LCDVD1 P4_4 LCDVD0 P4_1 ...
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... NXP Semiconductors Table 20. LCD panel connections for STN dual panel mode External pin 4-bit mono STN dual panel LPC18xx pin used LCDVD2 P4_3 LCDVD1 P4_4 LCDVD0 P4_1 LCDLP P7_6 LCDENAB/ P4_6 LCDM LCDFP P4_5 LCDDCLK P4_7 LCDLE P7_0 LCDPWR P7_7 GP_CLKIN PF_4 Table 21 ...
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... NXP Semiconductors Table 21. LCD panel connections for TFT panels External TFT 12 bit (4:4:4 mode) TFT 16 bit (5:6:5 mode) pin LPC18xx LCD pin used function LCDVD0 - - LCDLP P7_6 LCDLP LCDENAB/ P4_6 LCDENAB/ LCDM LCDM LCDFP P4_5 LCDFP LCDDCLK P4_7 LCDDCLK LCDLE P7_0 ...
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... NXP Semiconductors Table 22. Fundamental oscillation frequency 12 MHz 16 MHz 20 MHz Table 23. Fundamental oscillation frequency 15 MHz 20 MHz Fig 25. Slave mode operation of the on-chip oscillator Fig 26. Oscillator modes with external crystal model used for C LPC1850_30_20_10 Objective data sheet Recommended values for C X1/X2 components parameters) low frequency mode ...
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... NXP Semiconductors 13.3 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors C third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plain ...
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... NXP Semiconductors 14. Package outline LBGA256: plastic low profile ball grid array package; 256 balls; body ball A1 index area ball index area 2 4 DIMENSIONS (mm are the original dimensions) A UNIT max 0.45 1.1 0.55 mm 1.55 0.35 0.9 0.45 OUTLINE VERSION IEC SOT740 Fig 27. Package outline LBGA256 package sot740_2 ...
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... NXP Semiconductors 15. Abbreviations Table 24. Acronym ADC AES AHB APB API BOD CAN CMAC CSMA/CD DAC DMA ETB ETM GPIO IRC IrDA JTAG LCD LSB MAC MCU MIIM n.c. OTG PHY PLL PWM RMII SDRAM SPI SSI SSP TCP/IP UART ULPI USART ...
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... NXP Semiconductors 16. Revision history Table 25. Revision history Document ID LPC1850_30_20_10 v.1.2 Modifications: LPC1850_30_20_10 v.1 LPC1850_30_20_10 Objective data sheet Release date Data sheet status 20110217 Objective data sheet • RMII removed from description of pin functions ENET_RXD2, ENET_RXD3, ENET_ER. ENET_REF_CLK removed from pin function ENET_RX_CLK • ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... For sales office addresses, please send an email to: LPC1850_30_20_10 Objective data sheet own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Functional description . . . . . . . . . . . . . . . . . . 30 7.1 Architectural overview . . . . . . . . . . . . . . . . . . 30 7.2 ARM Cortex-M3 processor . . . . . . . . . . . . . . . 30 7.3 AHB multilayer matrix . . . . . . . . . . . . . . . . . . . 31 7 ...
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... NXP Semiconductors 10.2 Power consumption . . . . . . . . . . . . . . . . . . . . 58 11 Dynamic characteristics . . . . . . . . . . . . . . . . . 61 11.1 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 61 11.2 IRC and RTC oscillators . . . . . . . . . . . . . . . . . 62 2 11.3 I C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 11.4 SSP interface . . . . . . . . . . . . . . . . . . . . . . . . . 65 11.5 USB interface . . . . . . . . . . . . . . . . . . . . . . . . 68 11.6 Dynamic external memory interface . . . . . . . . 69 11.7 Static external memory interface . . . . . . . . . . 70 12 ADC/DAC electrical characteristics . . . . . . . . 73 13 Application information ...