ICS9EMS9633BKILF IDT, Integrated Device Technology Inc, ICS9EMS9633BKILF Datasheet - Page 5

• Manufacturer Part Number: ICS9EMS9633BKILF
• Description: IC EMBEDDED PC MAIN CLK 48VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of ICS9EMS9633BKILF

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN
• Frequency-max: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1949

MLF Pin Description
IDT
PIN #
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ICS9EMS9633
ULTRA MOBILE PC CLOCK FOR EMBEDDED APPLICATIONS
1
2
3
4
5
6
7
8
9
TM
/ICS
CPU_STOP#
CLKPWRGD#/PD_3.3
X2
X1
VDDREF_3.3
REF
GNDREF
VDDCORE_3.3
FSC_L
TEST_MODE
TEST_SEL
SCLK_3.3
SDATA_3.3
VDDCORE_3.3
VDDIO_1.5
DOT96C_LPR
DOT96T_LPR
GNDDOT
GNDLCD
LCD100C_LPR
LCD100T_LPR
VDDIO_1.5
VDDCORE_3.3
*CR#0
TM
Ultra Mobile PC Clock for Embedded Applications
PIN NAME
TYPE
PWR Power pin for the XTAL and REF clocks, nominal 3.3V
PWR Ground pin for the REF outputs.
PWR 3.3V power for the PLL core
PWR 3.3V power for the PLL core
PWR Power supply for low power differential outputs, nominal 1.5V.
PWR Ground pin for DOT clock output
PWR Ground pin for LCD clock output
PWR Power supply for low power differential outputs, nominal 1.5V.
PWR 3.3V power for the PLL core
OUT
OUT
OUT
OUT
OUT
OUT
I/O
IN
IN
IN
IN
IN
IN
IN
IN
Stops all CPU clocks, except those set to be free running clocks
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs
are valid and are ready to be sampled. This is an active low input. / Asynchronous
active high input pin used to place the device into a power down state.
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
14.318 MHz reference clock.
Low threshold input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values.
TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode
while in test mode. Refer to Test Clarification Table.
TEST_SEL: latched input to select TEST MODE
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
Complement clock of low power differential pair for 96.00MHz DOT clock. No 50ohm
resistor to GND needed. No Rs needed.
True clock of low power differential pair for 96.00MHz DOT clock. No 50ohm resistor
to GND needed. No Rs needed.
Complement clock of low power differential pair for LCD100 SS clock. No 50ohm
resistor to GND needed. No Rs needed.
True clock of low power differential pair for LCD100 SS clock. No 50ohm resistor to
GND needed. No Rs needed.
Clock request for SRC0, 0 = enable, 1 = disable
1 = All outputs are tri-stated for test
0 = All outputs behave normally.
5
DESCRIPTION
Datasheet
1617—08/19/09