IDTCSPU877ANLG8 IDT, Integrated Device Technology Inc, IDTCSPU877ANLG8 Datasheet - Page 6

• Manufacturer Part Number: IDTCSPU877ANLG8
• Description: IC PLL CLK DVR SDRAM 40-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Driverr

Specifications of IDTCSPU877ANLG8

• Input: Clock
• Output: Differential
• Frequency - Max: 340MHz
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN, 40-VFQFPN
• Frequency-max: 340MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: CSPU877ANLG8

TIMING REQUIREMENTS
NOTES:
1. 270MHz max clock frequency for parts assembled and tested prior to WW37.
2. The PLL will track a spread spectrum clock input.
3. Operating clock frequency is the range over which the PLL will lock, but may not meet all timing specifications. To be used only for low speed system debug.
4. Application clock frequency is the range over which timing specifications apply.
5. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up. During normal operation, the
AC ELECTRICAL CHARACTERISTICS
NOTES:
1. There are two different terminations that are used with the above AC tests. The output load shown in figure 1 is used to measure the input and output differential pair cross-voltage
2. Refers to transition of non-inverting output.
3. Period jitter and half-period jitter specifications are seperate specifications that must be met independently of each other.
4. To eliminate the impact of input slew rates on static phase offset, the input slew rates of reference clock input (CLK, CLK) and feedback clock input (FBIN, FBIN) are recommended
5. Static phase offset does not include jitter.
6. V
IDTCSPU877A
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
t
stabilization time is also the time required for the PLL circuit to obtain phase lock of its feedback signal to its reference signal when CLK and CLK go to a logic LOW state, enters
the power-down mode, and later return to active operation. CLK and CLK may be left floating after they have been driven LOW for one complete clock cycle.
The PLL on the CSPU877A will meet all the above test parameters while supporting SSC synthesizers with the following parameters:
only. The output load shown in figure 2 is used to measure all other tests, including input and output slew rates. For consistency, use 50Ω equal length cables with SMA connectors
on the test board.
to be nearly equal. The 2.5V/ns slew rates are shown as a recommended target. Compliance with these nominal values is not mandatory if it can be adequately demonstrated
that alternative characteristics meet the requirements of the registered DDR2 DIMM application.
t
JIT(HPER) (3)
t
Symbol
JIT(PER) (3)
SLR(O) (1,4)
t
SLR(I) (1,4)
Symbol
t
OX
t
t
V
JIT(CC+)
V
t
t
JIT(CC-)
(∅)DYN
t
t
SSC
SSC
PLH (2)
PHL (2)
(∅) (5)
SK(O)
ID(AC)
f
t
V
t
OX (6)
3dB
f
DIS
EN
CLK
t
is specified at the DDR DRAM clock input or test load.
DC
IX
t
L
Parameter
Operating Clock Frequency
Application Clock Frequency
Input Clock Duty Cycle
Stabilization Time
Description
LOW to HIGH Level Propagation Delay Time
HIGH to LOW Level Propagation Delay Time
Jitter (cycle-to-cycle)
Jitter (period)
Half-Period Jitter
Output Clock Slew Rate (single-ended)
Output Enable (OE)
Input Clock Slew Rate
Static Phase Offset
Dynamic Phase Offset
Output Skew
Output Enable to any Y or Y
Output Disable to any Y or Y
AC Differential Output Crosspoint Voltage
AC Differential Input Voltage
AC Differential Input Crosspoint Voltage
Modulation Frequency
Clock Input Frequency Deviation
PLL Loop Bandwidth
(5)
(1,2,3)
(2,4)
Test Conditions
A
CLK to any output
A
CLK to any output
166/200/266MHz
166/200/266MHz
166/200/266MHz
166/200/266MHz (20% to 80%)
166/200/266MHz
166/200/266MHz
Differential outputs terminated with 120Ω
VDD
VDD
= GND, OE = H, OS = L,
= GND, OE = H, OS = L,
(1)
6
Min.
125
160
⎯
40
(V
(V
DDQ
DDQ
COMMERCIAL TEMPERATURE RANGE
Min.
-40
-60
1.5
0.5
-50
-50
0.6
30
/2) -0.15
0
0
1
0
2
/2) -0.1
Typ.
TBD
TBD
2.5
2.5
⎯
⎯
⎯
Max.
340
340
60
15
(2)
(V
(V
V
DDQ
DDQ
DDQ
Max.
-0.5
-40
⎯
/2) +0.15
40
40
60
50
50
40
33
3
4
8
8
/2) +0.1
+0.4
MHz
MHz
Unit
%
μs
MHz
V/ns
V/ns
KHz
Unit
ns
ns
ps
ps
ps
ps
ps
ps
ns
ns
%
V
V
V