ICS97U2A877AHLFT IDT, Integrated Device Technology Inc, ICS97U2A877AHLFT Datasheet
ICS97U2A877AHLFT
Specifications of ICS97U2A877AHLFT
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ICS97U2A877AHLFT Summary of contents
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Integrated Circuit Systems, Inc. 1.8V Low-Power Wide-Range Frequency Clock Driver Recommended Application: • DDR2 Memory Modules / Zero Delay Board Fan Out • Provides complete DDR DIMM logic solution with ICSSSTU32864/SSTUF32864/SSTUF32866/ SSTUA32864/SSTUA32866/SSTUA32S868/ SSTUA32S865/SSTUA32S869 Product Description/Features: • Low skew, low jitter ...
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ICS97U2A877A Advance Information Pin Descriptions ...
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Function Table ...
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ICS97U2A877A Advance Information Absolute Maximum Ratings Supply Voltage (VDDQ & AVDD -0.5V to 2.5V Logic Inputs . . . . . . . . . . . . . . . ...
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Recommended Operating Condition (see note1 -40°C - 85°C; Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) A PARAMETER SYMBOL Supply Voltage V DDQ Low level input voltage V High level input voltage V DC ...
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ICS97U2A877A Advance Information Timing Requirements 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) A PARAMETER SYMBOL Max clock frequency Application Frequency Range Input clock duty cycle CLK stabilization NOTE: The PLL ...
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Switching Characteristics 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) A PARAMETER SYMBOL Output enable time Output disable time Period jitter t Half-period jitter Input slew rate Output clock slew ...
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ICS97U2A877A Advance Information Figure 1. IBIS Model Output Load VDD/2 ICS97U2A877A -VDD FB_OUTC FB_OUTT X 1180—11/14/05 Parameter Measurement Information (CLKC) V (CLKC) ICS97U2A877A GND GND R = ...
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CLK_INC CLK_INT FB_INC FB_INT FB_OUTC FB_OUTT FB_OUTC FB_OUTT FB_OUTC FB_OUTT X 1180—11/14/05 Advance Information Parameter Measurement Information t ...
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ICS97U2A877A Advance Information Y , FB_OUTC FB_OUTT X 20% Clock Inputs and Outputs 1180—11/14/05 Parameter Measurement Information t jit(hper_n) t jit(hper_n+ jit(hper) jit(hper_n) 2xf O Figure 7. Half-Period Jitter ...
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CK CK FBIN FBIN t ( )dyn Figure 10. Time delay between OE and Clock Output (Y, Y) 1180—11/14/ SSC OFF SSC )dyn Figure 9. Dynamic Phase Offset ...
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ICS97U2A877A Advance Information - Place the 2200pF capacitor close to the PLL. - Use a wide trace for the PLL analog power & ground. Connect PLL & caps to AGND trace & connect trace to one GND via (farthest from ...
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A1 D TOP VIEW E ALL DIMENSIONS IN MILLIMETERS Min/Max 7.00 Bsc 4.50 Bsc 0.86/1.00 0.65 Bsc Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used. * Source Ref.: JEDEC ...
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ICS97U2A877A Advance Information Index Area Top View D THERMALLY ENHANCED, VERY THIN, FINE PITCH BASIC D2 M IN. / MAX IN. / MAX. L MIN. / ...