IDTCV141PAG8 IDT, Integrated Device Technology Inc, IDTCV141PAG8 Datasheet - Page 3

• Manufacturer Part Number: IDTCV141PAG8
• Description: IC CLK BUFFER 1-8 DIFF 48-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Bufferr

Specifications of IDTCV141PAG8

• Input: Clock
• Output: Clock
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency-max: -
• Other names: CV141PAG8

PIN DESCRIPTION
INDEX BLOCK WRITE PROTOCOL
INDEX BYTE WRITE
Setting bit[11:18] = starting address, bit[20:27] = 01h.
IDTCV141
1-TO-8 DIFFERENTIAL CLOCK BUFFER
11-18
20-27
29-36
38-45
DIF_[7:0], DIF_ [7:0]#
Bit
2-9
SRC_IN, SRC_IN#
10
19
28
37
46
1
PLL/Bypass#
SRC_DIV2#
HIGH_BW#
SRC_STOP
Pin Name
OE_INV
OE[7:0]
P
LOCK
IREF
WRDWN
SDA
SCL
# of bits
1
8
1
8
1
8
1
8
1
8
1
Master
Master
Master
Master
Master
Master
Master
Master
Slave
Slave
Slave
Slave
Slave
From
Slave
I/O, Open Collector
OUT, DIF
IN, DIF
Type
OUT
I N
IN
I N
IN
IN
I N
I N
IN
IN
Start
DCh
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Byte count, N (0 is not valid)
Ack (Acknowledge)
first data byte (Offset data byte)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
:
Nth data byte
Acknowledge
Stop
Description
8, 9, 12, 13, 16, 17,
20, 21, 29, 30, 33,
34, 37, 38, 41, 42
35, 36, 43, 44
6, 7, 14, 15,
Pin #
4,5
26
46
45
22
28
27
23
24
40
1
0.7V differential SRC input
0.7V differential clock output
3.3V LVTTL input for enabling differential outputs (see OE_INV table)
3.3V LVTTL for power down (see OE_INV table)
Reference current for differential output
HIGH, locked
1 = PLL mode, 0 = bypass, PLL OFF
0 = HIGH BW, 1 = LOW BW (see HIGH_BW# Selection table)
LOW = divide by 2 mode
SRC stop (see OE_INV table)
SMBus clock
SMBus data
(see OE_INV table)
3
INDEX BLOCK READ PROTOCOL
Master can stop reading any time by issuing the stop bit without waiting
until Nth byte (byte count bit30-37).
INDEX BYTE READ
Setting bit[11:18] = starting address. After reading back the first data byte,
master issues Stop bit.
11-18
21-28
30-37
39-46
48-55
Bit
2-9
10
19
20
29
38
47
1
# of bits
1
8
1
8
1
1
8
1
8
1
8
1
8
Description
Master
Master
Master
Master
Master
Master
Master
Master
Master
From
Slave
Slave
Slave
Slave
Slave
Slave
Slave
COMMERCIAL TEMPERATURE RANGE
Start
DCh
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Repeated Start
DDh
Ack (Acknowledge)
Byte count, N (block read back of N
Ack (Acknowledge)
first data byte (Offset data byte)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
Ack (Acknowledge)
Nth data byte
Not acknowledge
Stop
bytes), power on is 8
:
Description