ICS97ULP877AHT IDT, Integrated Device Technology Inc, ICS97ULP877AHT Datasheet
ICS97ULP877AHT
Specifications of ICS97ULP877AHT
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ICS97ULP877AHT Summary of contents
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Integrated Circuit Systems, Inc. 1.8V Low-Power Wide-Range Frequency Clock Driver Recommended Application: • DDR2 Memory Modules / Zero Delay Board Fan Out • Provides complete DDR DIMM logic solution with ICSSSTU32864/SSTUF32864/SSTUF32866/ SSTUA32864/SSTUA32866/SSTUA32S868/ SSTUA32S865/SSTUA32S869 Product Description/Features: • Low skew, low jitter ...
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ICS97ULP877A Pin Descriptions ...
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Function Table ...
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ICS97ULP877A Absolute Maximum Ratings Supply Voltage (VDDQ & AVDD -0.5V to 2.5V Logic Inputs . . . . . . . . . . . . . . . . . ...
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Recommended Operating Condition (see note1 70°C; Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) A PARAMETER SYMBOL Supply Voltage V DDQ Low level input voltage V High level input voltage V DC ...
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ICS97ULP877A Timing Requirements 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) A PARAMETER Max clock frequency Application Frequency Range Input clock duty cycle CLK stabilization NOTE: The PLL must be able ...
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Switching Characteristics 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) A PARAMETER SYMBOL Output enable time Output disable time Period jitter t Half-period jitter Input slew rate Output clock slew ...
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ICS97ULP877A ICS97ULP877A Z = 60Ω 2.97" 60Ω 2.97" Yx, FB_OUTC Yx, FB_OUTT 7116—03/27/07 Parameter Measurement Information V DD ICS97ULP877A GND IBIS Model Output Load C = 10pF GND ...
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CLK_INC CLK_INT FB_INC FB_INT Yx Yx Yx, FB_OUTC Yx, FB_OUTT Yx, FB_OUTC Yx, FB_OUTT Yx, FB_OUTC Yx, FB_OUTT 0981C—04/05/05 Parameter Measurement Information t (∅)n Σ (∅) (∅ large number ...
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ICS97ULP877A Yx, FB_OUTC Yx, FB_OUTT 20% Clock Inputs and Outputs 7116—03/27/07 Parameter Measurement Information t JIT(HPER_n JIT(HPER) JIT(HPER_n) Half-Period Jitter 80% t SLR Input and Output Skew Rates 10 t JIT(HPER_n+1) 1 2xfo 80% V ...
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CLK CLK FBIN FBIN SSC OFF SSC ON t (Ø)DYN 50 Y Time Delay Between OE and Clock Output (Y, Y) 0981C—04/05/05 Parameter Measurement Information t (Ø) t (Ø)DYN Dynamic Phase Offset DDQ ...
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ICS97ULP877A R1 VIA CARD V DDQ 1Ω GND VIA CARD - Place the 2200pF capacitor close to the PLL. - Use a wide trace for the PLL analog power & ground. Connect PLL & caps to AGND trace & connect ...
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SEATING PLANE A1 D TOP VIEW E ALL DIMENSIONS IN MILLIMETERS Min/Max 7.00 Bsc 4.50 Bsc 0.86/1.00 0.65 Bsc Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used. * Source ...
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ICS97ULP877A Index Area Top View D THERMALLY ENHANCED, VERY THIN, FINE PITCH BASIC D2 MIN. / MAX. E2 MIN. / MAX. L MIN. / MAX. Source Reference: MLF2™ ...