ICS9212AF-13T IDT, Integrated Device Technology Inc, ICS9212AF-13T Datasheet
ICS9212AF-13T
Manufacturer Part Number
ICS9212AF-13T
Description
IC CLK GEN DIRECT RAMBUS 24-SSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Direct RAMbus Clock Generatorr
Datasheet
1.ICS9212AF-13LFT.pdf
(7 pages)
Specifications of ICS9212AF-13T
Output
Clock
Frequency - Max
600MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
24-SSOP
Frequency-max
600MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Input
-
Other names
9212AF-13T
General Description
The ICS9212-13 is a High-speed clock generator providing
up to 600 MHz differential clock source for direct Rambus™
memory system. It includes DDLL (Distributed Delay
locked loop) and phase detection mechanism to
synchronize the direct Rambus™ channel clock to an
external system clock. ICS9212-13 provides a solution for
a broad range of Direct Rambus memory applications. The
device works in conjunction with the ICS9250-09.
The ICS9212-13 power management support system
turns “off” the Rambus™ channel clock to minimize power
consumption for mobile and other power–sensitive
applications. In “clock off” mode the device remains “on”
while the output is disabled, allowing fast transitions
between clock-off and clock–on states. In “power down”
mode it completely powers down for minimum power
dissipation.
The ICS9212-13 meets the requirements for input frequency
tracking when the input frequency clock is using Spread
Spectrum clocking and also the optimum bandwidth is
maintained while attenuating the jitter of the reference
signal.
Block Diagram
0272F—08/08/07
BUSCLK_STOP#
Direct Rambus™ Clock Generator
Multi(0:1)
Synclk/N
FS(0:1)
Pclk/M
Refclk
PD#
2
Integrated
Circuit
Systems, Inc.
GND
B
A
Test MUX
PLLclk
PLL
Bypass MUX
Detector
Aligner
Phase
Phase
PAclk
Bypclk
GND
BUSCLKC
Features
•
•
•
•
•
•
•
BUSCLKT
Compatible with all Direct Rambus™ based IC s
Up to 600 MHz differential clock source for direct
Rambus™ memory system
Cycle to cycle jitter is less than 40ps
3.3 + 5% supply
Synchronization flexibility: Supports Systems that
need clock domains of Rambus channel to
synchronize with system or processor clock, or
systems that do not require synchronization of the
Rambus clock to another system clock
Excellent power management support
REFCLK input is from the ICS9250-09.
BUSCLK_STOP#
SYNCLK/N
VDDREF
REFCLK
PCLK/M
VDDPD
GND1
GND3
GND2
VDD1
VDD2
PD#
Pin Configuration
24-Pin 150 Mil SSOP
10
11
12
1
2
3
4
5
6
7
8
9
ICS9212-13
24
23
22
21
20
19
18
17
16
15
14
13
FS0
FS1
VDD-OUT
GND-OUT
BUSCLKT
N/C
BUSCLKC
GND-OUT
VDD-OUT
MULTI0
MULTI1
FS2
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ICS9212AF-13T Summary of contents
Page 1
Integrated Circuit Systems, Inc. Direct Rambus™ Clock Generator General Description The ICS9212- High-speed clock generator providing up to 600 MHz differential clock source for direct Rambus™ memory system. It includes DDLL (Distributed Delay locked loop) and phase detection ...
Page 2
ICS9212-13 Pin Descriptions Pin # Name 1 VDDREF 2 REFCLK 3 VDD1 4 GND1 5 GND3 6,7 PCLK/M, SYNCLK/N 8 GND2 9 VDD2 10 VDDPD 11 BUSCLK_ STOP# 12 PD# 14,15 MULTI (0:1) 16 VDD_OUT 17 GND_OUT 18 BUSCLKC 19 ...
Page 3
PLL Divider Selection and PLL Values (PLLCLK = REFCLK*A/B) Multo Mult1 Bypass and Test Mode Selection Mode FS0 Normal 0 Bypass 1 Test 1 Vendor Test A ...
Page 4
ICS9212-13 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V Logic Inputs . . . . . ...
Page 5
Recommended Layout General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance. Capacitor Values: ...
Page 6
ICS9212- ...
Page 7
Revision History Rev. Issue Date Description F 08/08/07 Fixed typo on Electrical Characteristics. 0272F—08/08/07 7 ICS9212-13 Page # 4 ...