ICS95V842AFLF IDT, Integrated Device Technology Inc, ICS95V842AFLF Datasheet - Page 5

• Manufacturer Part Number: ICS95V842AFLF
• Description: IC DVR DDR PLL 16-QSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Driverr

Specifications of ICS95V842AFLF

• Input: Clock
• Output: Clock
• Frequency - Max: 333MHz
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP
• Frequency-max: 333MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 95V842AFLF

Notes:
0830B—11/24/08
Switching Characteristics
T
Max clock frequency
Application Frequency
Range
Input clock duty cycle
Input clock slew rate
CLK stabilization
Low-to high level propagation
delay time
High-to low level propagation
delay time
Output enable time
Output disable time
Period jitter
Half-period jitter
Output clock slew rate
Cycle to Cycle Jitter
Static Phase Offset
Output to Output Skew
A
= 0°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
1.
2.
3.
4. Does not include jitter.
3
Refers to transition on noninverting output in PLL bypass mode.
While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=twH/tc,
were the cycle (tc) decreases as the frequency goes up.
Switching characteristics are guaranteed for application frequency range. The
PLL Locks over the Max Clock Frequency range, but the device doe not
necessarily meet other timing parameters.
PARAMETER
3
SYMBOL
freq
t
freq
t
T
t
cyc
t
t
jit(hper)
jit (per)
t
t
t
PLH
PHL
t
d
(spo)
skew
STAB
t
t
sl(o)
sl(I)
dis
en
-t
tin
App
op
cyc
1
1
CLK_IN to any output
CLK_IN to any output
PD# to any output
PD# to any output
Over the application
frequency range
CONDITION
5
MIN
-75
-75
-75
-50
40
60
40
1
1
TYP
40
5
5
ICS95V842
MAX
333
220
100
5.5
5.5
2.5
60
75
75
75
50
60
2
UNITS
MHz
MHz
v/ns
v/ns
µs
ns
ns
ns
ns
ps
ps
ps
ps
ps
%