ICS9DB1200CGLF IDT, Integrated Device Technology Inc, ICS9DB1200CGLF Datasheet - Page 5

• Manufacturer Part Number: ICS9DB1200CGLF
• Description: IC BUFFER 12OUTPUT DIFF 64-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Bufferr
• Series: -r

Specifications of ICS9DB1200CGLF

• Input: Differential
• Output: Differential
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 9DB1200CGLF

Absolute Max
Electrical Characteristics - Input/Supply/Common Output Parameters
IDT
T
Operating Supply Current
1
2
3
Tambient
ESD prot
Guaranteed by design and characterization, not 100% tested in production.
See timing diagrams for timing requirements.
Time from deassertion until outputs are >200 mV
Symbol
A
Modulation Frequency
ICS9DB1200C
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
Tcase
VDDA
TM
VDD
Powerdown Current
= 0 - 70°C; Supply Voltage V
Input High Voltage
PLL Jitter Peaking
Input High Current
Input Low Voltage
Input Low Current
V
V
Ts
/ICS
Input Frequency
Clk Stabilization
Pin Inductance
PLL Bandwidth
IL
IH
PARAMETER
OE# Latency
Capacitance
Tdrive_PD
TM
Trise
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
Tfall
3.3V Logic Supply Voltage
3.3V Core Supply Voltage
Ambient Operating Temp
Storage Temperature
Input ESD protection
human body model
Input High Voltage
Case Temperature
Input Low Voltage
Parameter
SYMBOL
F
I
I
t
DD3.3OP
t
DD3.3PD
iBYPASS
T
LATOE#
F
C
j
DRVPD
f
PEAK
BW
V
L
C
V
I
I
MOD
STAB
I
iPLL
t
IL1
IL2
OUT
t
IH
pin
R
IH
IN
F
IL
DD
= 3.3 V +/-5%
V
clock stabilization or de-assertion of
PLL Bandwidth when HIGH_BW#=0
PLL Bandwidth when HIGH_BW#=1
IN
From V
V
DIF stop after OE# deassertion
= 0 V; Inputs with pull-up resistors
IN
Peaking when HIGH_BW#=0
Peaking when HIGH_BW#=1
DIF start after OE# assertion
all differential pairs tri-stated
Full Active, C
= 0 V; Inputs with no pull-up
Output pin capacitance
DIF output enable after
Triangular Modulation
DD
Rise time of OE#
PD# to 1st clock
Fall time of OE#
PD de-assertion
GND-0.5
Power-Up and after input
CONDITIONS
Bypass Mode
3.3 V +/-5%
3.3 V +/-5%
Logic Inputs
2000
PLL Mode
V
Min
-65
resistors
IN
0
= V
L
= Full load;
DD
V
5
DD
Max
150
115
4.6
4.6
+0.5V
70
GND - 0.3
-200
MIN
100
Units
1.5
0.7
33
30
-5
-5
2
2
4
°
°C
°C
V
V
V
V
V
C
TYP
1.5
1.5
3
1
V
DD
MAX
375
400
400
300
0.8
1.4
1.8
24
33
12
+ 0.3
5
7
5
6
2
2
4
5
5
UNITS NOTES
cycles
MHz
MHz
MHz
MHz
kHz
mA
mA
ms
uA
uA
uA
nH
dB
dB
pF
pF
us
ns
ns
V
V
1414E—11/04/09
1,2
1,3
1,3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1