ICS9DB403DGILF IDT, Integrated Device Technology Inc, ICS9DB403DGILF Datasheet - Page 14
![IC BUFFER 4OUTPUT DIFF 28-TSSOP](/photos/6/91/69166/28-ssop_pyg28_sml.jpg)
ICS9DB403DGILF
Manufacturer Part Number
ICS9DB403DGILF
Description
IC BUFFER 4OUTPUT DIFF 28-TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Bufferr
Series
-r
Datasheet
1.ICS9DB403DFLFT.pdf
(19 pages)
Specifications of ICS9DB403DGILF
Input
HCSL
Output
HCSL, LVDS
Frequency - Max
400MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-TSSOP
Frequency-max
400MHz
Number Of Elements
1
Supply Current
225mA
Pll Input Freq (min)
50MHz
Pll Input Freq (max)
110MHz
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Package Type
TSSOP
Output Frequency Range
50 to 100MHz
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.465V
Operating Temperature Classification
Industrial
Pin Count
28
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
9DB403DGILF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ICS9DB403DGILF
Manufacturer:
Micrel
Quantity:
156
Company:
Part Number:
ICS9DB403DGILFT
Manufacturer:
TI
Quantity:
5 325
Note: Polarities in timing diagrams are shown OE_INV = 0. They are similar to OE_INV = 1.
PD#, Power Down
The PD# pin cleanly shuts off all clocks and places the device into a power saving mode. PD# must be asserted before shutting
off the input clock or power to insure an orderly shutdown. PD is asynchronous active-low input for both powering down the
device and powering up the device. When PD# is asserted, all clocks will be driven high, or tri-stated (depending on the PD#
drive mode and Output control bits) before the PLL is shut down.
PD# Assertion
When PD# is sampled low by two consecutive rising edges of DIF#, all DIF outputs must be held High, or tri-stated (depending
on the PD# drive mode and Output control bits) on the next High-Low transition of the DIF# outputs. When the PD# drive mode
bit is set to ‘0’, all clock outputs will be held with DIF driven High with 2 x I
set to ‘1’, both DIF and DIF# are tri-stated.
PD# De-assertion
Power-up latency is less than 1 ms. This is the time from de-assertion of the PD# pin, or VDD reaching 3.3V, or the time from
valid SRC_IN clocks until the time that stable clocks are output from the device (PLL Locked). If the PD# drive mode bit is set
to ‘1’, all the DIF outputs must driven to a voltage of >200 mV within 300 us of PD# de-assertion.
IDT
ICS9DB403D
Four Output Differential Buffer for PCIe for Gen 1 and Gen 2
TM
/ICS
TM
Four Output Differential Buffer for PCIe Gen 1 and Gen 2
PWRDWN#
PWRDWN#
DIF#
DIF#
DIF
DIF
Tstable
<1mS
<300uS, >200mV
Tdrive_PwrDwn#
14
REF
and DIF# tri-stated. If the PD# drive mode bit is
ICS9DB403D
REV M 01/27/11