ICS932S200BFLFT IDT, Integrated Device Technology Inc, ICS932S200BFLFT Datasheet

ICS932S200BFLFT

Manufacturer Part Number

ICS932S200BFLFT

Description

IC FREQ TIMING GENERATOR 56-SSOP

Manufacturer

IDT, Integrated Device Technology Inc

Type

Frequency Generatorr

Datasheet

1.ICS932S200BFLFT.pdf (13 pages)

Specifications of ICS932S200BFLFT

Input

Crystal

Output

Clock

Frequency - Max

133MHz

Voltage - Supply

3.135 V ~ 3.465 V

Operating Temperature

0°C ~ 70°C

Mounting Type

Surface Mount

Package / Case

56-SSOP

Frequency-max

133MHz

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Other names

932S200BFLFT

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Frequency Timing Generator for Dual Server/Workstation Systems

0427D—12/15/08

General Description

The ICS932S200 is a dual CPU clock generator for

serverworks HE-T, HE-SL-T, LE-T chipsets for P III type

processors in a Dual-CPU system. Single ended CPU

clocks provide faster than 1.5V/ns transition times by

parallel connection of 2 CPU pins to each processor.

Spread Spectrum may be enabled by driving the

SPREAD# pin active. Spread spectrum typically

reduces system EMI by 8dB to 10dB. This simplifies

EMI qualification without resorting to board design

iterations or costly shielding. The ICS932S200 employs

a proprietary closed loop design, which tightly controls

the percentage of spreading over process and

temperature variations.

Key Specification:

•

SEL 133/100#

CPU_STOP#

Block Diagram

PCI_STOP#

SPREAD#

CPU Output Jitter: 150ps

IOAPIC Output Jitter: 250ps

3V66, PCI Output Jitter: 250ps

CPU Output Skew: <175ps

PCI Output Skew: <500ps

3V66 Output Skew <250ps

IOAPIC Output Skew <250ps

CPU to 3V66 Output Offset: 0 - 1.5ns (CPU leads)

CPU to PCI Output Offset: 1.5 - 4.0ns (CPU leads)

CPU to APIC Output Offset: 1.5 - 4.0ns (CPU

leads)

SEL0

SEL1

PD#

Integrated

Circuit

Systems, Inc.

XTAL

OSC

Spectrum

PLL2

Spread

Control

Config.

PLL1

Logic

Reg.

DIVDER

IOAPIC

3V66

CPU

PCI

Stop

48MHz

IOAPIC (2:0)

PCICLK (4:0)

PCICLK_F

3V66 (1:0)

CPUCLK (5:0)

REF (1:0)

Features

•

Generates the following system clocks:

33MHz)

Efficient power management through PD#,

CPU_STOP# and PCI_STOP#.

0.5% typical down spread modulation on CPU, PCI,

IOAPIC and 3V66 output clocks.

Uses external 14.318MHz crystal.

- 6 CPU clocks ( 2.5V, 100/133MHz)

- 6 PCI clocks, including 1 free running(3.3V,

- 3 IOAPIC clocks (2.5V, 16.67MHz)

- 2 Fixed frequency 66MHz clocks(3.3V, 66MHz)

- 2 REF clocks(3.3V, 14.318MHz)

- 1 USB clock (3.3V, 48MHz)

SEL 133/100#

PCICLK_F

PCICLK0

PCICLK1

PCICLK2

PCICLK3

PCICLK4

3V66_0

3V66_1

REF0

REF1

GND

VDD

56-pin 240 mil TSSOP

56-pin 300 mil SSOP

Pin Configuration

ICS932S200

VDDL

IOAPIC2

IOAPIC1

IOAPIC0

GND

VDDL

CPUCLK5

CPUCLK4

GND

VDDL

CPUCLK3

CPUCLK2

GND

VDDL

CPUCLK1

CPUCLK0

GND

VDD

GND

PCI_STOP#

CPU_STOP#

PD#

SPREAD#

SEL1

SEL0

VDD

48MHz

GND

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ICS932S200BFLFT Summary of contents

Page 1

Integrated Circuit Systems, Inc. Frequency Timing Generator for Dual Server/Workstation Systems General Description The ICS932S200 is a dual CPU clock generator for serverworks HE-T, HE-SL-T, LE-T chipsets for P III type processors in a Dual-CPU system. Single ended CPU clocks ...

Page 2

ICS932S200 Pin Descriptions Pin number Pin name 13, 19 20, 21, 24, 29, GND PWR 38, 40, 44, 48 REF(1:0) OUT 4,. 10, 16, 17, 22, 23, 27, 31, VDD PWR ...

Page 3

Frequency Select ...

Page 4

ICS932S200 Power Management Requirements ...

Page 5

PCI_STOP# Timing Diagram PCI_STOP input to the clock synthesizer and must be made synchronous to the clock driver PCICLK_F output used to turn off the PCI clocks for low power operation. PCI clocks are required to ...

Page 6

ICS932S200 PD# Timing Diagram The power down selection is used to put the part into a very low power state without turning off the power to the part. PD asynchronous active low input. This signal needs to be ...

Page 7

Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . ...

Page 8

ICS932S200 Electrical Characteristics - CPUCLK 70º 3.3 V +/-5 PARAMETER SYMBOL Output High Voltage V OH2B Output Low Voltage V OL2B Output High Current I OH2B Output Low Current I ...

Page 9

Electrical Characteristics - PCICLK 70º 3.3 V +/-5 PARAMETER SYMBOL Output High Voltage V OH1 Output Low Voltage V OL1 Output High Current I OH1 Output Low Current I OL1 ...

Page 10

ICS932S200 Electrical Characteristics - 48MHz, REF 70º 3.3 V +/-5 PARAMETER SYMBOL Output High Voltage V OH5 Output Low Voltage V OL5 Output High Current I OH5 Output Low Current ...

Page 11

SSOP Ordering Information 932S200yFT Example: XXXX PPP T Designation for tape and reel packaging Pattern Number ( digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate ...

Page 12

ICS932S200 INDEX INDEX AREA AREA 6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil) Ordering Information 932S200yGT Example: XXXX PPP T Designation ...

Page 13

Revision History Rev. Issue Date Description D 12/15/2008 Removed ICS prefix from ordering information 0427D—12/15/08 13 ICS932S200 Page # 11-12 ...

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