ICS932S203AGLF IDT, Integrated Device Technology Inc, ICS932S203AGLF Datasheet - Page 15

• Manufacturer Part Number: ICS932S203AGLF
• Description: IC FREQ GEN W/CPU CLOCK 56-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Frequency Generatorr
• Series: -r

Specifications of ICS932S203AGLF

• Input: Crystal
• Output: Clock
• Frequency - Max: 133.3MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 133.3MHz
• Number Of Elements: 2
• Supply Current: 360mA
• Pll Input Freq (min): 14.318MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSSOP
• Output Frequency Range: 66.66 to 133.3MHz
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Pin Count: 56
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 932S203AGLF

IDT
ICS932S203
Frequency Generator with 133MHz Differential CPU Clocks
TM
Frequency Generator with 133MHz Differential CPU Clocks
PD# - Assertion (transition from logic "1" to logic "0")
When PD# is sampled low by two consecutive rising edges of CPU clock then all clock outputs except CPU clocks must be
held low on their next high to low transition. CPU clocks must be held with the CPU clock pin driven high with a value of 2x Iref,
and CPUC undriven. Note the example below shows CPU = 100MHz, this diagram and description is applicable for all valid
CPU frequencies 66, 100, 133, 200MHz.
Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one
clock cycle to complete.
PD# Functionality
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CPUT 100MHz
CPUC 100MHz
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USB 48MHz
66MHz_OUT
PCI 33MHz
66MHz_IN
3V66MHz
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Power Down Assertion of Waveforms - Buffered Mode
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