ICS950908BGLF IDT, Integrated Device Technology Inc, ICS950908BGLF Datasheet - Page 4

• Manufacturer Part Number: ICS950908BGLF
• Description: IC TIMING CTRL HUB P4 56-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Timing Control Hubr

Specifications of ICS950908BGLF

• Input: Crystal
• Output: Clock
• Frequency - Max: 200MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 950908BGLF

Pin Description Continued
Mode Pin - Power Management Input Control
0653A—07/26/04
PIN
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
#
L (
M
PIN
NAME
DDRC5/SDRAM11
DDRT5/SDRAM10
DDRC4/SDRAM9
DDRT4/SDRAM8
GND
VDD3.3_2.5
DDRC3/SDRAM7
DDRT3/SDRAM6
DDRC2/SDRAM5
DDRT2/SDRAM4
GND
VDD3.3_2.5
DDRC1/SDRAM3
DDRT1/SDRAM2
DDRC0/SDRAM1
DDRT0/SDRAM0
BUF_IN
FBOUT
GND
CPUT1_CS
CPUT0_CS
VDDCPU2.5
VDDCPU3.3
CPUCLKC/CPUCLKODC
CPUCLKT/CPUCLKODT
GND
VDDREF
Vtt_PWRGD#**/REF1
a
O
c t
Integrated
Circuit
Systems, Inc.
D
h
, E
e
0
1
d
P
n I
n i
p
u
6
) t
R
(
TYPE
O
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
OUT
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
(
P
PIN
E
I/O
n I
P
IN
n i
u
S
D
p
p t
E
u
2
#
u
T
6
) t
) t
#
"Complimentary" Clock of differential memory output / 3.3V SDRAM clock output
"True" Clock of differential memory output / 3.3V SDRAM clock output
"Complimentary" Clock of differential memory output / 3.3V SDRAM clock output
"True" Clock of differential memory output / 3.3V SDRAM clock output
Ground pin.
2.5V or 3.3V nominal power supply voltage.
"Complimentary" Clock of differential memory output / 3.3V SDRAM clock output
"True" Clock of differential memory output / 3.3V SDRAM clock output
"Complimentary" Clock of differential memory output / 3.3V SDRAM clock output
"True" Clock of differential memory output / 3.3V SDRAM clock output
Ground pin.
2.5V or 3.3V nominal power supply voltage.
"Complimentary" Clock of differential memory output / 3.3V SDRAM clock output
"True" Clock of differential memory output / 3.3V SDRAM clock output
"Complimentary" Clock of differential memory output / 3.3V SDRAM clock output
"True" Clock of differential memory output / 3.3V SDRAM clock output
Input Buffers for memory outputs.
Memory feed back output.
Ground pin.
Power pin for the CPUCLKs. 2.5V
Power pin for the CPUCLKs. 3.3V
"Complementary" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias / "Complementary" clocks of
differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up /
2.5V CPU clock output.
"True" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias / "True" clocks of differential pair CPU
outputs. These open drain outputs need an external 1.5V pull-up / 2.5V CPU clock
output.
Ground pin.
Ref, XTAL power supply, nominal 3.3V
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs
are valid and are ready to be sampled. This is an active low input. / 14.318 MHz
reference clock.
True clock of differential pair 2.5V push-pull CPU outputs.
True clock of differential pair 2.5V push-pull CPU outputs.
C
P
4
P
(
U
O
P
(
C
n I
_
n i
C I
u
S
p
p t
u
1
T
L
u
8
) t
K
O
) t
5
P
#
Preliminary Product Preview
DESCRIPTION
P
C
(
O
(
_ I
A
P
n I
G
u
n i
S
p
p t
P
T
u
8
u
O
2
) t
) t
P
#
ICS950908