ICS87604AGILFT IDT, Integrated Device Technology Inc, ICS87604AGILFT Datasheet - Page 8

• Manufacturer Part Number: ICS87604AGILFT
• Description: IC CLK GEN PCI/PCI-X 28-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Clock Multiplier, Zero Delay Bufferr

Specifications of ICS87604AGILFT

• Input: LVCMOS, LVTTL
• Output: LVCMOS, LVTTL
• Frequency - Max: 167MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Frequency-max: 167MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 87604AGILFT

ICS87604I
O
The XTAL_IN input can be overdriven by an LVCMOS driver or by
one side of a differential driver through an AC coupling capacitor.
The XTAL_OUT pin can be left floating. The amplitude of the input
signal should be between 500mV and 1.8V and the slew rate
should not be less than .2V/nS. For 3.3V LVCMOS inputs, the
amplitude must be reduced from full swing to at least half the
swing in order to prevent signal interference with the power rail
and to reduce internal noise. Figure 3A shows an example of the
interface diagram for a high speed 3.3V LVCMOS driver. This
configuration requires that the sum of the output impedance of
the driver (Ro) and the series resistance (Rs) equals the
transmission line impedance. In addition, matched termination at
the crystal input will attenuate the signal in half. This can be done
ICS87601AGI REVISION B APRIL 1, 2010
F
F
IGURE
VERDRIVING THE
IGURE
3.3V
Driv er_LVCMOS
3A. G
VCC=3.3V
3B. G
Ro ~ 7 Ohm
LVPECL
ENERAL
ENERAL
RS
C
D
D
RYSTAL
IAGRAM FOR
IAGRAM FOR
43
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
I
NTERFACE
R2
50
LVCMOS D
LVPECL D
R1
100
R2
100
R1
50
R3
50
3.3V
RIVER TO
RIVER TO
C1
0.1uF
C1
0.1uF
XTAL_IN
XTAL_OUT
XTAL I
XTAL I
XTAL_IN
XTAL_OUT
Cry stal Input Interf ace
Cry stal Input Interf ace
NPUT
NPUT
8
LOW VOLTAGE/LOW SKEW, 1:4 PCI/PCI-X ZERO DELAY CLOCK GENERATOR
I
I
in one of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50 applications, R1 and
R2 can be 100 . This can also be accomplished by removing R1
and changing R2 to 50 . The values of the resistors can be
increased to reduce the loading for slower and weaker LVCMOS
driver. Figure 2 shows an example of the interface diagram for an
LVPECL driver. This is a standard LVPECL termination with one
side of the driver feeding the XTAL_IN input. It is recommended
that all components in the schematics be placed in the layout.
Though some components might not be used, they can be utilized
for debugging purposes. The datasheet specifications are
characterized and guaranteed by using a quartz crystal as the
input.
NTERFACE
NTERFACE
2010 Integrated Device Technology, Inc.