ICS932S208DF IDT, Integrated Device Technology Inc, ICS932S208DF Datasheet - Page 17

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ICS932S208DF

Manufacturer Part Number
ICS932S208DF
Description
IC TIMING HUB CTRL PROGR 56-SSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Timing Control Hubr
Datasheet

Specifications of ICS932S208DF

Input
Crystal
Output
Clock
Frequency - Max
200MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-SSOP
Frequency-max
200MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
932S208DF

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PD# De-assertion
The time from the de-assertion of PD# or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive
mode control bit for PD# tristate is programmed to '1' the stopped differential pair must first be driven high to a minimum of
200mV in less than 300 s of PD# deassertion.
3V66_4/VCH Pin Functionality
The 3V66_4/VCH pin can be configured to be a 66.66MHz modulated output or a non-spread 48MHz output. The default is
3V66 clock. The switching is controlled by Byte 5 Bit 5. If it is set to '1' this pin will output the 48MHz VCH clock. The output
will go low on the falling edge of 3V66 for a minimum of 7.49ns. Then the output will transition to 48MHz on the next rising
edge of DOT_48 clock.
IDT
ICS932S208
Programmable Timing Control Hub
TM
Programmable Timing Control Hub
CPU#, 133MHz
3V66_4/VCH
SRC# 100MHz
REF, 14.31818
CPU, 133MHz
SRC, 100MHz
3V66, 66MHz
USB, 48MHz
PCI, 33MHz
PWRDWN#
DOT_48
3V66
TM
for Next Gen P4
TM
for Next Gen P4
TM
<1.8mS
Tstable
Processor
TM
<300µS, >200mV
Tdrive_PwrDwn#
Processor
17
7.49nS min
0743G—01/26/10

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