W256H Cypress Semiconductor Corp, W256H Datasheet - Page 5

• Manufacturer Part Number: W256H
• Description: IC CLK BUFF 12OUT SDRAM 28SSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Buffer (Distribution)r

Specifications of W256H

• Number Of Circuits: 1
• Ratio - Input:output: 1:12
• Differential - Input:output: No/No
• Input: DDR, SDRAM
• Output: DDR, SDRAM
• Frequency - Max: 180MHz
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Frequency-max: 180MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1399

Document #: 38-07256 Rev. *C
Switching Characteristics
Switching Waveforms
Notes:
–
–
t
t
t
t
t
t
t
t
Duty Cycle Timing
All Outputs Rise/Fall Time
Output-Output Skew
4. All parameters specified with loaded outputs.
5. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1V/ns.
Parameter
3
4
3d
4d
5
6
7
8
OUTPUT
OUTPUT
OUTPUT
Duty Cycle
SDRAM Rising Edge Rate
SDRAM Falling Edge Rate
DDR Rising Edge Rate
DDR Falling Edge Rate
Output to Output Skew
Output t4o Output Skew for
SDRAM
SDRAM Buffer HH Prop. Delay
SDRAM Buffer LLProp. Delay
Operating Frequency
0.4V
t
3
2.4V
t
5
[2]
[4,5]
Name
= t
t
2
2
÷ t
[4]
1
t
[4]
[4]
1
[4]
2.4V
0.4V
[4]
[4]
t
4
[4]
[4]
Measured at 1.4V for 3.3V outputs
Measured at VDD/2 for 2.5V outputs.
Measured between 0.4V and 2.4V
Measured between 2.4V and 0.4V
Measured between 20% to 80% of
output (Refer to Figure 1)
Measured between 20% to 80% of
output (Refer to Figure 1)
All outputs equally loaded
All outputs equally loaded
Input edge greater than 1 V/ns
Input edge greater than 1 V/ns
Test Conditions
3.3V
0V
IN
Min.
–5%
1.0
1.0
0.5
0.5
66
5
5
DC
Typ.
IN
DC
Max.
2.50
2.50
1.50
1.50
180
100
150
10
10
+5%
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W256
MHz
V/ns
V/ns
V/ns
V/ns
Unit
ns
ns
ps
ps
%