ICS854104AGLF IDT, Integrated Device Technology Inc, ICS854104AGLF Datasheet - Page 11

• Manufacturer Part Number: ICS854104AGLF
• Description: IC FANOUT BUFF DIFF-LVDS 16TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Fanout Buffer (Distribution)r

Specifications of ICS854104AGLF

• Number Of Circuits: 1
• Ratio - Input:output: 1:4
• Differential - Input:output: Yes/Yes
• Input: HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: LVDS
• Frequency - Max: 700MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 700MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1183; 800-1183-5; 800-1183; 854104AGLF

ICS854104 Data Sheet
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS854104.
Equations and example calculations are also provided.
1.
The total power dissipation for the ICS854104 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The
following is the power dissipation for V
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature for HiPerClockS devices is 125°C. Limiting the internal transistor junction temperature, Tj, to
125°C ensures that the bond wire and bond pad temperature remains below 125°C.
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
a multi-layer board, the appropriate value is 100.3°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance
ICS854104AG REVISION A AUGUST 14, 2009
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
Power Dissipation.
•
70°C + 0.260W * 100.3°C/W = 96.1°C. This is well below the limit of 125°C.
Power (core)
The equation for Tj is as follows: Tj = θ
Tj = Junction Temperature
θ
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
JA
A
= Ambient Temperature
= Junction-to-Ambient Thermal Resistance
MAX
= V
DD_MAX
θ
JA
* I
DD
for 16 Lead TSSOP, Forced Convection
DD_MAX
= 3.3V + 5% = 3.465V, which gives worst case results.
JA
= 3.465V * 75mA = 259.875mW
* Pd_total + T
θ
JA
A
100.3°C/W
by Velocity
0
11
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
96.0°C/W
JA
1
must be used. Assuming no air flow and
©2009 Integrated Device Technology, Inc.
93.9°C/W
2.5