ICS854S204BGILF IDT, Integrated Device Technology Inc, ICS854S204BGILF Datasheet - Page 12
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ICS854S204BGILF
Manufacturer Part Number
ICS854S204BGILF
Description
IC CLK FANOUT BUFFER 1:2 16TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
HiPerClockS™r
Type
Fanout Buffer (Distribution)r
Datasheet
1.ICS854S204BGILF.pdf
(19 pages)
Specifications of ICS854S204BGILF
Number Of Circuits
2
Ratio - Input:output
1:2
Differential - Input:output
Yes/Yes
Input
CML, LVDS, LVPECL, SSTL
Output
LVDS, LVPECL
Frequency - Max
3GHz
Voltage - Supply
2.375 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-TSSOP
Frequency-max
3GHz
Number Of Outputs
8
Operating Supply Voltage (max)
3.465V
Operating Temp Range
-40C to 85C
Propagation Delay Time
0.5ns
Operating Supply Voltage (min)
2.375V
Mounting
Surface Mount
Pin Count
16
Operating Supply Voltage (typ)
2.5/3.3V
Package Type
TSSOP
Duty Cycle
51%
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
800-1964-5
854S204BGILF
ICS854S204BGILF
854S204BGILF
ICS854S204BGILF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ICS854S204BGILF
Manufacturer:
IDT Integrated Device Technolo
Quantity:
135
Company:
Part Number:
ICS854S204BGILF
Manufacturer:
IDT
Quantity:
4 990
T
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50
IDT
3.3V, 2.5V LVDS D
A general LVDS interface is shown in Figure 3. In a 100
differential transmission line environment, LVDS drivers
require a matched load termination of 100
ERMINATION FOR
ICS854S204I
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
RTT =
™
transmission lines. Matched impedance techniques should
/ ICS
™
((V
F
LVDS, LVPECL FANOUT BUFFER
FOUT
OH
IGURE
+ V
OL
4A. LVPECL O
) / (V
1
3.3V LVPECL O
CC
RIVER
Z
Z
– 2)) – 2
o
o
= 50
= 50
T
Z
ERMINATION
o
VDD
50
UTPUT
LVDS_Driv er
UTPUTS
T
100 Ohm Differential Transmission Line
F
RTT
ERMINATION
IGURE
50
V
CC
3. T
across near
FIN
- 2V
YPICAL
LVDS D
12
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
unused outputs.
be used to maximize operating frequency and minimize signal
distortion. Figures 4A and 4B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
RIVER
R1
100
T
FOUT
ERMINATION
F
IGURE
4B. LVPECL O
+
-
Z
Z
2.5V or 3.3V
o
o
= 50
= 50
ICS854S204BGI REV. A JUNE 4, 2008
125
84
UTPUT
3.3V
125
84
T
ERMINATION
FIN