NB6L14MNG ON Semiconductor, NB6L14MNG Datasheet - Page 2

• Manufacturer Part Number: NB6L14MNG
• Description: IC FANOUT BUFFER DIFF 1:4 16-QFN
• Manufacturer: ON Semiconductor
• Series: ECLinPS MAX™r
• Type: Fanout Buffer (Distribution)r

Specifications of NB6L14MNG

• Number Of Circuits: 1
• Ratio - Input:output: 1:4
• Differential - Input:output: Yes/Yes
• Input: CML, LVCMOS, LVDS, LVPECL, LVTTL
• Output: LVCMOS, LVPECL
• Frequency - Max: 3GHz
• Voltage - Supply: 2.375 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TFQFN Exposed Pad
• Frequency-max: 3GHz
• Number Of Outputs: 8
• Max Input Freq: 3000 MHz
• Propagation Delay (max): 0.5 ns @ 2.375V to 3.63V
• Supply Voltage (max): 3.63 V
• Supply Voltage (min): 2.375 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 47 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: NB6L14MNG; NB6L14MNGOS

1. In the differential configuration when the input termination pin VT, is connected to a common termination voltage or left open, and if no signal
Table 1. EN TRUTH TABLE
Table 2. PIN DESCRIPTION
+ = On next negative transition of the input signal (IN).
x = Don’t care.
is applied on IN/IN inputs, then the device will be susceptible to self−oscillation.
Q1
Q1
Q2
Q2
Pin
10
12
13
14
15
16
11
1
2
3
4
5
6
7
8
9
−
1
2
3
4
IN
0
1
x
Figure 2. QFN−16 Pinout
VREF_AC
Q0
Q3
16
Name
5
GND
V
V
EN
Q1
Q1
Q2
Q2
Q3
Q3
VT
Q0
Q0
EP
IN
IN
CC
CC
(Top View)
Q0
15
Q3
6
V
V
14
CC
7
CC
LVTTL/LVCMOS
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL, CML,
LVPECL, CML,
LVDS, HSTL
LVDS, HSTL
GND
13
EN
8
I/O
−
−
−
−
IN
1
0
x
12
10
11
9
IN
VT
VREF_AC
IN
Exposed Pad (EP)
Non−inverted Differential Output. Typically Terminated with 50 W Resistor to
V
Inverted Differential Output. Typically Terminated with 50 W Resistor to V
Non−inverted Differential Output. Typically Terminated with 50 W Resistor to
V
Inverted Differential Output. Typically Terminated with 50 W Resistor to V
Non−inverted Differential Output. Typically Terminated with 50 W Resistor to
V
Inverted Differential Output. Typically Terminated with 50 W Resistor to V
Positive Supply Voltage
Synchronous Output Enable. When LOW, Q outputs will go LOW and Q outputs will
go HIGH on the next negative transition of IN input. The internal DFF register is
clocked on the falling edge of IN input (see Figure 20). The EN pin has an internal
pullup resistor and defaults HIGH when left open.
Inverted Differential Clock Input. Internal 50 W Resistor to Termination Pin, VT.
Output Voltage Reference for capacitor−coupled inputs, only.
Internal 100 W center−tapped Termination Pin for IN and IN.
Non−inverted Differential Clock Input. Internal 50 W Resistor to Termination Pin, VT.
Negative Supply Voltage
Positive Supply Voltage
Noninverted Differential Output. Typically Terminated with 50 W Resistor to
V
Inverted Differential Output. Typically Terminated with 50 W Resistor to V
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the
die for improved heat transfer out of package. The exposed pad must be attached to
a heat−sinking conduit. The pad is not electrically connected to the die, but is
recommended to be electrically and thermally connected to GND on the PC board.
CC
CC
CC
CC
–2.0 V.
–2.0 V.
– 2.0 V.
– 2.0 V.
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VREF_AC
EN
1
1
0
2
EN
VT
/IN
IN
50 W
50 W
Description
Q0:Q3
0+
0
1
D
CLK
Figure 3. Logic Diagram
Q
Q0:Q3
1+
1
0
CC
CC
CC
CC
–2.0 V.
– 2.0 V.
– 2.0 V.
– 2.0 V.
Q0
/Q0
Q1
/Q1
Q2
/Q2
Q3
/Q3