ICS854057AGLF IDT, Integrated Device Technology Inc, ICS854057AGLF Datasheet
ICS854057AGLF
Specifications of ICS854057AGLF
800-1181-5
800-1181
854057AGLF
Related parts for ICS854057AGLF
ICS854057AGLF Summary of contents
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Integrated Circuit Systems, Inc ENERAL ESCRIPTION The ICS854057 is a 4:1 or 2:1 LVDS Clock Mul- ICS tiplexer which can operate up to 2GHz and is a HiPerClockS™ member of the HiPerClockS™ family of High Per- formance Clock ...
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Integrated Circuit Systems, Inc ABLE IN ESCRIPTIONS ...
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Integrated Circuit Systems, Inc BSOLUTE AXIMUM ATINGS Supply Voltage Inputs, V -0. Outputs Continuous Current 10mA Surge Current 15mA Package Thermal Impedance, JA Storage Temperature, T -65°C to 150°C STG ...
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Integrated Circuit Systems, Inc. T 4D. LVDS DC C ABLE HARACTERISTICS ...
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Integrated Circuit Systems, Inc. The spectral purity in a band at a specific offset from the funda- mental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise ...
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Integrated Circuit Systems, Inc. P ARAMETER V DD 2.5V±5% POWER SUPPLY LVDS + - Float GND 2. UTPUT OAD EST IRCUIT nPCLKx PCLKx nPCLKy PCLKy PD2 t PD1 tsk(i) tsk( ...
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Integrated Circuit Systems, Inc. 80% Clock 20% Outputs UTPUT ISE ALL IME V DD LVDS DC Input ➤ FFSET OLTAGE ETUP 854057AG 4 80% LVDS DC Input V ...
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Integrated Circuit Systems, Inc. 2.5V LVDS D T RIVER ERMINATION Figure 1 shows a typical termination for LVDS driver in charac- teristic impedance of 100 differential (50 2.5V LVDS_Driv er 2. IFFERENTIAL NPUT WITH To prevent oscillation ...
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Integrated Circuit Systems, Inc. LVPECL NPUT WITH UILT N The PCLK /nPCLK with built-in 50 LVDS, LVPECL, LVHSTL, CML, SSTL and other differential signals. Both V and V must meet the V SWING OH input ...
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Integrated Circuit Systems, Inc ECOMMENDATIONS FOR NUSED I : NPUTS PCLK/nPCLK I : NPUT For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, but ...
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Integrated Circuit Systems, Inc ABLE VS IR LOW ABLE FOR JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in ...
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Integrated Circuit Systems, Inc ACKAGE UTLINE UFFIX FOR T ABLE Reference Document: JEDEC Publication 95, MO-153 854057AG 4:1 OR TSSOP EAD ACKAGE IMENSIONS ...
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Integrated Circuit Systems, Inc ABLE RDERING NFORMATION ...